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QS74FCT648CTZ Datasheet

With most applications, the offset strap is not utilized and can be ignored. Designers can leave one or both strap connections (O- and Off+) open circuited, or ground one connection node. Do not tie both strap connections together to avoid shorted turn magnetic circuits.
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Capacitors	(Murata 0402)	Inductors	(Toko)
Cextl	2 pF	Lext1	18 nH LL1005
Cext2	1 nF	Lext2	270 nH LL1608
Cext3	20 pF	Lext3	220 nH LL1608
Cext4	100 pF	Lext4	12 nH LL1005
Cext5	1 nF	Lexts	15 nH LL1005
Cext6	1 nF
Cext7	3.3 pF
Cext8	100 nF	Lext8	22 nH LL1005

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Parameter	80RIA	U nits	Conditions
PGM Maximum peak gate power	12		Tj = Tj max, tp " 5ms
PG(AV) Maximum average gate power	3	W	Tj = Tj max, f = 50Hz, d% = 50
IGM Max. peak positive gate current	3	A	Tj = Tj max, tp " 5ms
+VGM Maximum peak positive gate voltage	20	V	Tj = Tj max, tp " 5ms
-VGM Maximum peak negative gate voltage	10	V	Tj = Tj max, tp " 5ms
IGT Max. DC gate current required to trigger	270 120 60	mA	Tj = - 400C Tj = 250C Max. required gate trigger/ cur- Tj = 1250C rent/voltage are the lowest value
VGT Max. DC gate voltage required to trigger	3 5 2 5 1 5	V	which will trigger all units 6V an- Tj = - 400C ode-to-cathode applied Tj = 250C Tj = 1250C
IGD DC gate current not to trigger	6	mA	Max. gate current/ voltage not to trigger is the max. value which
VGD DC gate voltage not to trigger	0 25	V	Tj = Tj max will not trigger any unit with rated VDRM anode-to-cathode applied

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