| Part Numbert | Mfg | Packt | D/C | Descriptiont | Qty | Company/Contact | |
| QT160DG | QUANTUM | 07/08+ | 2396 |
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QT160DG Datasheet
QT160DG on stock TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express orimplied, is granted underany patent right, copyright, maskwork right, orother intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI's publication of information regarding any third party's products or services does not constitute TI's approval, warranty or endorsement thereof. Write Write operations are initiated when both CE and WE are LOW and OE is HIGH. The XM28C020 supports both a CE and WE controlled write cycle. That is, the address is latched by the falling edge of either CE or WE, whichever occurs last. Similarly, the data is latched internally by the rising edge of either CE or WE, which- ever occurs first. A byte write operation, once initiated, will automatically continue to completion, typicallywithin 5ms (see Note 4). |