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QU80486SXSF25 Datasheet

CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
QU80486SXSF25 Price


A15 [ A14 [ A13 [ A12 [ A11 [ CE [ 1/00 [ 1/01 [ l/02 [ l/03 [ Vcc [ GND [ 1/04 [ 1/05 [ l/06 [ 1/07 [ WE [ A10 [ A9 [ A8 [ A7 [ NC [	44 2 43 3 42 4 41 5 40 6 39 7 38 8 37 9 36 10 35 11 34 12 33 13 32 14 31 15 30 16 29 17 28 18 27 19 26 20 25 21 24 22 23	] AO ] A1 ] A2 ] OE ] UB ] LB ] 1/015 ] l/014 ] l/013 ] 1/012 ] GND ] Vcc ] 1/011 ] 1/010 ] l/09 ] l/08 ] NC ] A3 ] A4 ] A5 ] A6 ] NC

QU80486SXSF25 on stock

Type	max. alternatmg input voltage	Repetitive peak reverse voltage
Typ	max. Eingangswechselspannung	Periodische Spitzensperrspannung
Typ	VVRMS [V]	VRRM [V]1)
GBU 6A	35	50
GBU 6B	70	100
GBU 6D	140	200
GBU 6G	280	400
GBU 6J	420	600
GBU 6K	560	800
GBU 6M	700	1000

		TEST CONDITIONS
SYMBOL	PARAMETER	WAVEFORMS	VCC (V)	MIN	TYP	MAX	UNIT
1w	shift clock pulse width HIGH or LOW	see Fig.7	4.5	20			ns
	storage clock pulse width HIGH or LOW	see Fig.8	4.5	20			ns
	master reset pulse width LOW	see Fig.10	4.5	25			ns
tsu	set-up time DS to SH_CP	see Fig.9	4.5	20			ns
tsu	set-up time SH CP to ST CP	see Fig.8	4.5	20			ns
th	hold time DS to SH CP	see Fig.9	4.5	3			ns
trem	removal time MR to SH CP	see Fig.10	4.5	13			ns
fmax	maximum clock pulse frequency SH CP or ST CP	see Figs 7 and 8	4.5	24			MHz
Tamb = -40 to +125 IC
tPHL/tPLH	propagation delay SH CP to QT	see Fig.7	4.5			63	ns
tPHL/tPLH	propagation delay ST CP to Qn	see Fig.8	4.5			60	ns
tPHL	propagation delay MR to QT	see Fig.10	4.5			60	ns
tPZH/tPZL	3-state output enable time OE to Qn	see Fig.ll	4.5			53	ns
tPHZ/tPLZ	3-state output disable time OE to Qn	see Fig.ll	4.5			45	ns
1w	shift clock pulse width HIGH or LOW	see Fig.7	4.5	24			ns
	storage clock pulse width HIGH or LOW	see Fig.8	4.5	24			ns
	master reset pulse width LOW	see Fig.10	4.5	30			ns
tsu	set-up time DS to SH_CP	see Fig.9	4.5	24			ns
tsu	set-up time SH CP to ST CP	see Fig.8	4.5	24			ns
th	hold time DS to SH CP	see Fig.9	4.5	3			ns
trem	removal time MR to SH CP	see Fig.10	4.5	15			ns
fmax	maximum clock pulse frequency SH CP or ST CP	see Figs 7 and 8	4.5	20			MHz

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