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Data transfer to and from the timekeeping function is accomplished with a serial bit stream under control of chip enable (CE), output enable (OE), and write enable (WE). Initially, a read cycle to any memory location using the CE and OE control of the phantom clock starts the pattern-recognition sequence by moving a pointer to the first bit of the 64-bit comparison register. Next, 64 consecutive write cycles are executed using the CE and WE signals ofthe device. These 64 write cycles are used only to gain access to the phantom clock. Therefore, any address within the first 512kB of memory, (OOh t0 7FFFFh) is acceptable. However, the write cycles generated to gain access to the phantom clock are also writing data to a location in the memory. The preferred way to manage this requirement is to set aside just one address location in memory as a phantom clock scratch pad. When the first write cycle is executed, it is compared to bit o of the 64-bit comparison register. If a match is found, the pointer increments to the next location of the comparison register and awaits the next write cycle. If a match is not found, the pointer does not 3 0f17
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