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On-chip PLLs use external RC-based loop tilters to allow custom tailoring ot loop response and support the wide range ot reference clock trequencies tound in SONET/SDH/ATM systems. For transmit clock synthesis or tor CDR the PLLs exceed ANSI, Bellcore, and ITU jitter specitications tor systems when combined with industry-typical O/E devices such as Sumitomo, AT&T, HP, and AMP. The T08105/T08106 PLLs provide byte clocks and constant- rate 38.88 MHz and 51.84 MHz, synthesized clock outputs, providing clocking tor UTOPIA and other system busses. Transmit data may also be clocked into the devices with respect to the reterence clock.