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QXO-28.6363MHZC Datasheet

Pin Number Pin Name Pin Type Pin Description
1 Xl/ICLK Input Crystal connection or clock input.
2 VDD Power Connect to +3.3 V or +5 V.
3 GND Power Connect to ground.
4 Sl Tri-Ievel linput Select l for output clock. Connect to GND or VDD or float.
5 CLK Output Clock output per table above.
6 SO Tri-Ievel Input Select o for output clock. Connect to GND or VDD or float.
7 OE Input Output enable. Tri-states CLK output when low. Internal pull-up.
8 X2 Output Crystal connection. Leave unconnected for clock input.


QXO-28.6363MHZC Price
These dual 4-bit registers feature 3-state outputs designed specifically for bus driving. This makes these devices particularly suitable for implementing buffer registers, l/0 ports, bidirectional bus drivers, and working registers. The dual 4-bit latches are transparent D-type. When the latch enable input (1C or 2C) is hIgh, the (Q) outputs will follow the data (D) inputs in true farm, according to the function table. When the latch enable input is_taken low, the outputs will be latched. When LR goes low, the Q outputs go low independently of enable C. The outputs are in a high-impedance state when Oc (output control) is at a high logic level. The 54AC11873 is characterized for operation over the full military temperature range of -550c t0 125'C. The 74AC11873 is characterized for operation from -400C to 850c.
QXO-28.6363MHZC on stock

SYMBOL PARAMETER CONDITIONS MIN TYP. MAX UNIT
Supply; pins 4, 5 and 18
VDD digital supply voltage VDDl=VDD2 2.7 5.5 V
Vcc analog supply voltage VccVDD 2.7 5.5 V
IDD synthesizer digital supply current VDD= 5.5 V 6.5 8.5 mA
lcc charge pumps and analog supply current Vcc = 5.5 V; Rext =12 kl 1.2 2.0 mA
ICCPD, IDDPD current in power-down mode per supply logic levels o or VDD 12 50
RF main divider input; pin 6
fvco RF input frequency 2.7 V < VDD < 3.5 V 50 1 250 MHz
2.7 V < VDD < 5.5 V 50 1 100 MHz
V6(rms) AC-coupled input signal level (RMS value) Rs = 50 1; 2.7 V < VDD < 3.5 V; 0.5 < fvco < 1.25 GHz; Tamb = -20 to +85 IC 50 225 mV
Rs = 50 1; 2.7 V < VDD < 5.5 V; 0.5 < fvco < 1.1 GHz; Tamb = -30 to +85 IC 100 300 mV
Rs = 50 1; 2.7 V < VDD < 5.5 V; 50 < fvco < 500 MHz; Tamb = -30 to +85 IC 150 300 mV
Zl input impedance (real part) fvco=1 GHz 1 kl
Cl typical pin input capacitance indicative, not tested 2 pF
Rm main divider ratio 512 131 071
fPCmax maximum phase comparator frequency 2000 kHz
fPCmin minimum phase comparator frequency 10 kHz
Crystal reference divider input; pin 8
fXTAL crystal reference input frequency 5 40 MHz
V8(rms) sinusoidal input signal level 4.0 V < VDD < 5.5 V 50 500 mV
(RMS value) 2.7 V < VDD < 5.5 V 50 250 mV
Zl input impedance (real part) fXTAL = 30 MHz 6 kl
Cl typical pin input capacitance indicative, not tested 2 pF
R reference divider ratio 8 2047


Power Dissipation The first equation below indicates the maximum power dissipation point for a package that has two power amplifiers operating at identical known supply voltages and loads with sine wave inputs: PIC(DISS) = (VCC)2/(#2RL) [W] For example, with a 5V power supply and a load of 161 , the maximum power dissipation of the amplifiers alone is 317mW. The additional power dissipation due to the 100mA reg- ulator operating at maximum current is nominally 170mW, but will increase if the output is reduced exter- nally from its nominal 3.3V. The regulator power con- sumption is given by: PREG = (VCC - VREG) x 100mA [W] To avoid thermal shutdown the sum of the regulator and amplifier power dissipation must not exceed the absolute maximum power-dissipation rating of the package.
 
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