R004F Datasheet| SYMBOL | PARAMETER | TEST CONDITIONS | LIMITS | UNIT | | MIN | MAX | | f | FREQUENCY RANGE | | 890 | 960 | MHz | | Po | OUTPUT POWER | VDD=12.5V,VGG=5V,Pin=lmW | 6 | | W | | Efficiency | TOTAL EFFICIENCY | VDD=12.5V, | 35 | | % | | 2fo | 2nd HARMONIC | Pout=6W (VGG adjust) | | -30 | dBc | | VSWR in | INPUT VSWR | Pin=lmW | | 4 | | | | LOAD VSWR TOLERANCE | VDD=15.2V,Pin=lmW,Po=6W(VGG adjust) 2c=50 0hms, LOAD VSWR=20:1 | No degradation or destroy | | | | | | | |
R004F Price * It is necessary to use DC blocking capacitors CRF and bypass capacitors Cbypass. *It is necessary to use control resistors RCTL, if current consumption needs to be reduced or ESD performance needs to be improved. * It is necessary to oprate at low frequency, DC blocking capacitors CRF needs higher valves. R004F on stock| Parameter | Description | Conditions | Min | Typ. | Max | Unit | | FPPM | Frequency Error | Part to Part, does not include PCB variation[8l | | +5 | ±10 | PPM | | Over commercial temperature range[9l | | +2 | +5 | PPM | | DC | Output Duty Cycle | Duty cycle for all outputs, measured at VDD/2 | 45 | 50 | 55 | % | | t3_54,2 5 | 54MOUT Rising Edge Slew Rate | 20% t0 80% of VDD54, VDD54 = 2.5V | 0.75 | 1.2 | 4.0 | V/ns | | 03_54, 1.675 | 54MOUT Rising Edge Slew Rate | 20% t0 80% of VDD54, VDD54 = 1.675V | 0.35 | 0.5 | 2.5 | V/ns | | t4_54,2 5 | 54MOUT Falling Edge Slew Rate | 80% t0 20% of VDD54, VDD54 = 2.5V | 0.75 | 1.2 | 4.0 | V/ns | | 04_54, 1.675 | 54MOUT Falling Edge Slew Rate | 80% t0 20% of VDD54, VDD54 = 1.675V | 0.35 | 0.5 | 2.5 | V/ns | | tCR, tCF | CLK/CLKB Rise and Fall Times | 20% t0 80% of output voltage | 160 | | 400 | ps | | oCRCF | CLK/CLKB Rise and Fall Diffe re n ce [1 0l | 20% t0 80% of output voltage | | | 100 | ps | | t5 | Lock Time[ll] | PLL lock time from power-up | | 1.0 | 3.0 | ms | | | | | | | |
PIN DESCRIPTION AO-A10 - Address Inputs DQO-DQ7 - Data In/Data Out CE - Chip Enable WE - Write Enable OE - Output Enable VCC - Power (+5V) GND - Ground
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