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R0068235 Datasheet

Symbol Ratings Test Condition(s) Min Typ Mx Unit
BDY23,180T2 2.0 V
VBE(SAT) Base-Emitter Voltage() lc=2.0 A, IB=0.25 A BDY24,181T2 1.2
BDY25,182T2 1.2
A 55
VCE=4 V, lc=l A B 65
Static Forward Current C 90
h21E A 1 5 20 45
transfer ratio() VCE=4 V, lc=2 A B 30 45 90
C 75 82 1 00
fT Transition Frequency VCE=15 V, lc=0.5 A, f=10 MHz BDY23,180T2 BDY24,181T2 BDY25,182T2 1 0 MHz
td+ tr Turn-on time lc=5 A, IB=1 A BDY23,180T2 BDY24,181T2 BDY25,182T2 0.3 0.5 06
ts+tf Turn-off time lc=5 A, IBi=l A, IB2=-0.5 A BDY23,180T2 BDY24,181T2 BDY25,182T2 1.5 2.0 0


R0068235 Price

l IIII GCl = 1 86V, RFIN = -40dBm, fLO = 1550MHz, jCBB = 20MHz,
j iBB
j
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R0068235 on stock

Va Req'd Rset Va Req'd Rset Va Req'd Rset
0 900 0pen 1 475 12.3 kl 2 55 216 k1
0 925 353 kl 1.50 11.6 kl 2 60 200 k1
0 950 175 kl 1.55 10.5 kl 2 65 185 k1
0 975 116 kl 1.60 9.49 kl 2 70 171 kl
1 000 85.9 k 1.65 8.64 kl 2 75 158 kl
1 025 68.0 k 1.70 7.90 kl 2 80 145 kl
1 050 56.2 k 1.75 7.24 kl 2 85 133 kl
1 075 47.7 k 1.80 6.66 kl 2 90 122 kl
1 100 41.3 k 1.85 6.14 kl 2 95 111 kl
1 125 36.4 k 1.90 5.67 kl 3 00 100 kl
1 150 32.4 k 1.95 5.25 kl 3 05 904 l
1 175 29.2 k 2.00 4.86 kl 3 10 810 l
1 200 26.5 k 2.05 4.51 kl 3 15 720 l
1 225 24.2 k 2 .10 4.19 kl 3 20 634 l
1 250 22.2 k 2 .15 3.89 kl 3 25 551 l
1 275 20.5 k 2.20 3.61 kl 3 30 473 l
1 300 19.0 k 2.25 3.36 kl 3 35 397 l
1 325 17.7 k 2.30 3.12 kl 3 40 324 l
1 350 16.6 k 2.35 2.90 kl 3 45 254 l
1 375 15.5 k 2.40 2.70 kl 3 50 187 l
1 400 14.6 k 2.45 2.51 kl 3 55 122 l
1 425 13.7 k 2.50 2.33 kl 3 60 60 l
1 450 13.0 k


Instructions are composed of up to six cycles. The first two cycles input a Coded Sequence to the Command Interface which is common to all in- structions (see Table 9). The third cycle inputs the instruction set-up command. Subsequent cycles output the addressed data or Electronic Signature for Read operations. In order to give additional data protection, the instructions for Program and Block or Chip Erase require further command in- puts. For a Program instruction, the fourth com- mand cycle inputs the address and data to be programmed. For an Erase instruction (block or chip), the fourth and fifth cycles input a further Coded Sequence before the Erase confirm com- mand on the sixth cycle. Erasure of a memory block may be suspended, in order to read data from another block or to program data in another block. and then resumed.