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Part Numbert	Mfg	Packt	D/C	Descriptiont	Qty	Company/Contact
R01908412	BOSS		08+/09+	全新原装，欢迎订购！	100	SHENG ZHOU HE ELECTRONICS CO.,.. Contact:zhou Tel:86-755-83397505.82883120 Fax:86-0755-88296852 Email: 1018686693@qq.com
R01908412	BOSS		2000		100	C & C Source Company Contact:su Tel:86-755-82565528 Fax: Email: sophia@ccsource.net

R01908412 Datasheet

DESCRIPTION The M36W108A is multi-chip device containing an 8 Mbit boot block Flash memory and a l Mbit of SRAM. The device is offered in the new Chip Scale Package solutions: LBGA48 1.Omm ball pitch and LGA48 1.Omm land pitch. The two components, of the package's overall 9 Mbit of memory, are distinguishable by use of the three chip enable lines: EF for the Flash memory, EIS and E2S for the SRAM.
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PARAMETER	SYMBOL	CONDITIONS		MIN TYP MAX	UNITS
Operating Voltage Range	Vcc	TA = OoC to +700C		1 0 5.5	V
		Vcc = 5.5V, no load		5 12
VCC Supply Current	lcc	Vcc = 3.6V, no load		4 10	UA
		TA= +25C		VTH - 1.8% VTH VTH + 1.8%	V
Reset Threshold (Note l)	VTH	TA = -400C to +850C		VTH - 2.5% VTH + 2.5%
Reset Threshold Tempco	CVTH/oC			60	ppm/oC
Vcc to Reset Delay		Vcc = falling at lmV/ps		35	US
		MAX6314US Dl-T		1 1.4 2
		MAX6314US D2-T		20 28 40
Reset Timeout Period	tRP	MAX6314US D3-T		140 200 280	ms
		MAX6314US D4-T		1120 1570 2240
MANUAL RESET INPUT
	VIL	VTH> 4.OV		O8	V
	VIH			2.4
MR Input Threshold	VIL	VTH< 4.OV		0.3 X Vcc
	VIH			0.7 X Vcc
MR Minimum Input Pulse				1	US
MR Glitch Rejection				100	ns
MR to Reset Delay				500	ns
MR Pull-Up Resistance				32 63 100	kl
		Vcc > 4.25V, ISINK = 3.2mA		0.4	V
		Vcc > 2.5V, ISINK = 1.2mA		O3
RESET Output Voltage	VOL	Vcc > 1.2V, ISINK = 0.5mA		O3
		Vcc > 1.OV, ISINK = 80pA		O3
RESETINTERNAL PULL-UP
Transition Flip-Flop Setup Time (Note 2)	tS			400	ns
Active Pull-Up Enable Threshold		Vcc= 5V		0.4 0.9	V
RESET Active Pull-Up Current		Vcc= 5V		20	mA
RESET Pull-Up Resistance				4.2 4.7 5.2	kl
			CLOAD = 120pF	333
RESET Output Rise Time	tR	Vcc= 3V	CLOAD = 250pF	666
(Note 3)			CLOAD = 200pF	333	ns
		Vcc= 5V	CLOAD = 400pF	666

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When an error happens in the nth page of the Block 'A' during erase or program operation. Copy the nth page data of the Block 'A' in the buffer memory to the nth page of another free block. (Block 'B') Then, copy the data in the lst ~ (n-l)th page to the same location of the Block 'B'. Do not further erase Block 'A' by creating an 'invalid Block' table or other appropriate scheme.

PIN	DESCRIPTION
1	emitter
2	base
3	collector, connected to case

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