| Parameter | Description | Test Conditions | Min | Typ | Max | Unit |
| 1t | Output Frequency | 30 pF load 10 pF load | 15 15 | | 100 133 | MHz |
| | Duty Cycle 9 = (t2/ ti) ' 100 | Measured at l.4 V, FOUT = 66.67 MHz | 40.0 | 50.0 | 60.0 | % |
| Duty Cycle 9 = (t2/ ti) ' 100 | Measured at l.4 V, FOUT < 50.0 MHz | 45.0 | 50.0 | 55.0 |
| t3 | Output Rise Time 9 | Measured between 0.8V and 2.OV | | | 1.50 | nS |
| t4 | Output Fall Time 9 | Measured between 2.OV and 0.8V | | | 1.50 | nS |
| t5 | Output-to-output skew 9 | All outputs equally loaded | | | 250 | pS |
| t6 | Delay, REF Rising Edge to CLKOUT Rising Edge 9 | Measured at VDD /2 | | 0 | ±350 | pS |
| t7 | Device-to-Device Skew 9 | Measured at VDD/2 0n the CLKOUT pins of the device | | 0 | 700 | pS |
| t8 | Output Slew Rate 9 | Measured between 0.8V and 2.OV using Test Circuit #2 | 1 | | | V/nS |
| tJ | Cycle-to-cycle jitter 9 | Measured at 66.67 MHz, loaded outputs | | | 200 | pS |
| tLOCK | PLL Lock Time 9 | Stable power supply, valid clock pre sented on REF pin | | | 1.0 | mS |
| | | | | | |
