| | | | | | 8 3ms Single Half Sine-Wave (JEDED Method) |
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R10E1Y2V185 on stock 2-WIRE BUS CHARACTERISTICS This bus is intended for communication between dierent ICs. It consists of two lines: one bi-direc- tional for data signals (SDA) and one for clock signals (SCL). Both the SDA and the SCL lines must be connected to a positive supply voltage via a pull-up resistor. The following protocol has been defined: - Data transfer may be initiated only when the bus is not busy. - During data transfer, the data line must remain stable whenever the clock line is High. - Changes in the data line while the clock line is High will be interpreted as control signals.
