| Pin | Type | Signal | Polarity | unction |
| CLK | Input | Pulse | Positive Edge | The system clock input. All of the SDRAM inputs are sampled on the rising edge of the clock. |
| CKE | Input | Level | Active High | Activates the CLK signal when high and deactivates the CLK signal when low, thereby initiates either the Power Down mode or the Self Refresh mode. |
| CS | Input | Pulse | Active Low | CS enables the command decoder when low and disables the command decoder when high. When the command decoder is disabled, new commands are ignored but previous operations continue. |
| RAS,CAS WE | Input | Pulse | Active Low | When sampled at the positive rising edge of the clock, AS, RAS, and WE define the command to be executed by the SDRAM. |
| AO - A11 | Input | Level | | During a Bank Activate command cycle, AO-A11 defines the row address (RAO-RA11) when sampled at the rising clock edge. During a Read or Write command cycle, AO-An defines the column address (CAO-CAn) when sampled at the rising clock edge.CAn depends from the SDRAM organization: 16M x 8 SDRAM CAO-CA9. In addition to the column address, A10(=AP) is used to invoke autoprecharge operation at the end of the burst read or write cycle. If Alo is high, autoprecharge is selected and BAO, BAl defines the bank to be precharged. If Alo is low, autoprecharge is disabled. During a Precharge command cycle, A10(=AP) is used in conjunction with BAO and BA1 to control which bank(s) to precharge. If A1 0 is high, all four banks will BAO and BAl are used to define which bank to precharge. |
| BAO, BA1 | Input | Level | | Selects which bank is to be active. |
| DQx | Input Output | Level | | Data Input/Output pins operate in the same manner as on conventional DRAMs. |
| DQM | Input | Pulse | Active High | The Data Input/Output mask places the DO buffers in a high impedance state when sam- pled high. In Read mode, DQM has a latency of two clock cycles and controls the output buffers like an output enable. In Write mode, DQM has a latency of zero and operates as a word mask by allowing input data to be written if it is low but blocks the write operation if DQM is high. One DQM input is present in x4 and x8 DRAMs. |
| VCC, VSS | Supply | | | Power and ground for the input buffers and the core logic. |
| VCCQ VSSQ | Supply | | | lsolated power supply and ground for the output buffers to provide improved noise immunity. |
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