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R1141Q191D Datasheet

			LImi
Parameter	Symbol	Test Condltfans	2SC2431			2SC2432			Unit
Parameter	Symbol	Test Condltfans	MirN	Typ	Max	Mn	Typ.	Ma}e	Unit
Collectar Cutoff Current	ICBO	VCB =120V, IE = 0			50				A
Collector Cutoff Current	lcao	VCB = 70V. JE = O						50	pA
Emitter Cutoff Current	IEa	VEB = 4V. Ie = O			50			50	pA
Collector CutoFf CurrenL	ICEO	Vce = 120V. lB - O			1				mA
Collectar Cutatf Currenr	lfiPO	VCE = 70A, la = O						1	mA
Collector to Basa Breakdown Voltage	V(BRICB	IC - 60 pA, IE -O	120			70			V
Emitteria Base Breakdawn Valfage	V(BR)ERO	rE = ImA, le - O	5			5			V
Callectar to Emitter Breakdo~vn Valtaga DC Current Galn	V(8R)CEO hFE1	Jc=lOmA, R8E =w VCE =.5V. lC - 1.5A '	120 35			70 35			V
DC Current Gain	hFEZ	VCE ~ SV, lC = 15A '	7			10
ColleOor to Emkter Saturation Voltage	VCEkat)	IC = 7A, lB = 0.7A t		0.4	t5		0.4	1.6	V
Ba!a to Emltter Saturation Voltage Qaln-Bandwjdth Praduee	VBEtsat)	VCE = 10V. lC = 1A		1.2 80	l.a		1.2 80	1.8	MHz
Output Capacitance Rlw Time	Cob tr	yCB b lOVi IE = O. f - 1MHz		200 0.20			200 0,20	oI	pF ps
Storage Tima	t¨g	IC = 7.5A, RL = 4fl Ial = -lB2 -. 0.76A		O70	1.0		0.70	1.0	,IS
Fal[ Tlme	tf	IC = 7.5A, RL = 4fl Ial = -lB2 -. 0.76A		0.12	0.8		0.12	0.8	}

R1141Q191D Price

Name	Description	SFR Address	Bit Functions and Addresses MSB LSB								Reset Value
			E7 E6 E5 E4 E3 E2 E1 EO
ACC*	Accumulator	EOh									OOh
AUXRl#	Auxiliary Function Register	A2h	KBF	BOD	BOI	LPEP	SRST	O		DPS	02hi
AUXRl#	Auxiliary Function Register	A2h	F7 F6 F5 F4 F3 F2 F1 FO								02hi
B*	B register	FOh									OOh
CMPl#	B register	ACh			CE1	CP1	CN1	OE1	C01	CMF1	OOhi
CMP2#	Comparator l control register	ADh			CE2	CP2	CN2	OE2	C02	CMF2	OOhi
DIVM# DPTR: DPH DPL	Comparator 2 control register CPU clock divide-by-M control Data pointer (2 bytes) Data pointer high byte Data pointer low byte	95h 83h 82h	CF CE CD CC CB CA C9 C8								OOh OOh OOh
12CFG#*	12C configuration register	C8h/RD	SLAVEN	MASTRQ	0	TIRUN			CT1	CTO	OOhi
		C8h/WR	SLAVEN	MASTRQ	CLRTI	TIRUN			CT1	CTO
		C8h/WR	DF DE DD DC DB DA D9 D8
12CON#*	12C control register	D8h/RD	RDAT	ATN	DRDY	ARL	STR	STP	MASTER		80hi
12CON#*	12C control register	D8h/WR	CXA	IDLE	CDR	CARL	CSTR	CSTP	XSTR	XSTP	80hi
12DAT#	12C data register	D9h/RD	RDAT	O	0	O	0	O	0	O	80h
		D9h/WR	XDAT	x	x	x	x	x	x	x
		D9h/WR	AF AE AD AC AB AA A9 A8
IENO*	Interrupt enable 0	A8h	EA	EWD	EBO	ES	ET1	EX1	ETO	EXO	OOh
IENO*	Interrupt enable 0	A8h	EF EE ED EC EB EA E9 E8								OOh
IENl#*	Interrupt enable 1	E8h	ETI		EC1			EC2	EKB	E12	OOhi
IENl#*	Interrupt enable 1	E8h	BF BE BD BC BB BA B9 88								OOhi
IPO*	Interrupt priority 0	B8h		PWD	PBO	PS	PT1	PX1	PTO	PXO	OOhi
IPOH#	Interrupt priority o high byte	B7h		PWDH	PBOH	PSH	PTIH	PXIH	PTOH	PXOH	OOhi
IPOH#	Interrupt priority o high byte	B7h	FF FE FD FC FB FA F9 F8								OOhi
IPl*	Interrupt priority 1	F8h	PTI		PC1			PC2	PKB	P12	OOhi
IPIH#	Interrupt priority l high byte	F7h	PTIH		PCIH			PC2H	PKBH	P12H	OOhi
KBI#	Keyboard Interrupt	86h	87 86 85 84 83 82 81 80								OOh
PO*	Port 0	80h	T1	CMP1	CMPREF	CINIA	CINIB	CIN2A	CIN2B	CMP2	Note 2
PO*	Port 0	80h	97 96 95 94 93 92 91 90								Note 2
P1*	Port 1	90h	(P1 7)	(P1 6)	RST	INT1	INTO	TO	RxD	TxD	Note 2
P1*	Port 1	90h	A7 A6 A5 A4 A3 A2 A1 AO								Note 2
P2*	Port 2	AOh							X1	X2	Note 2
POMl#	Port o output mode 1	84h	(POMl.7)	(POMl.6)	(POMl.5)	(POMl.4)	(POMl.3)	(POMl.2)	(POMl.1)	(POMl.0)	OOh
POM2#	Port o output mode 2	85h	(POM2.7)	(POM2.6)	(POM2.5)	(POM2.4)	(POM2.3)	(POM2.2)	(POM2.1)	(POM2.0)	OOH
PIMl#	Port l output mode 1	91h	(PIMl.7)	(PIMl.6)		(PIMl.4)			(PIMl.1)	(PIMl.0)	OOhi
PIM2#	Port l output mode 2	92h	(PIM2.7)	(P1 M2.6)		(P1 M2.4)			(PIM2.1)	(P1 M2.0)	OOhi
P2M1#	Port 2 0utput mode 1	A4h	P2S	PIS	POS	ENCLK	T10E	TOOE	(P2M1.1)	(P2M1.0)	OOh
P2M2#	Port 2 0utput mode 2	A5h							(P2M2.1)	(P2M2.0)	OOhi
PCON	Power control register	87h	SMOD1	SMODO	BOF	POF	GF1	GFO	PD	IDL	Note 3

R1141Q191D on stock

AO-A16	Address Inputs
DQO-DQ7	Data Input/Output
E1	Chip Enable
E2	Chip Enable
G	Output Enable
	Write Enable
Vcc	Supply Voltage
Vss	Ground

binary-weighted currents of magnitude IFS/32, IFS/64 and IFS/128 to the outputs. The seven least-significant bits steer identical IFS/1 28 currents into a differential R-2R ladder to generate effective bit currents of IFS/256 to IFS/16384. The DAC output is the sum of the outputs of the segments and the low-order bits.

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