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R1141Q371B Datasheet
R1141Q371B Price These megacell generators are complemented by a group of application specific embedded megacells. These allow access to technologies that have been hitherto the domain of standard products. Examples include mixed mode cells for graphics, DAC/ADC's (4-9 bit), PLL applications, and Digital Signal Processor functions for cellular comms, fax and high-speed modems, which initially consist of a Triple 8-bit DAC, Graphics RAM, Clock Multiplier PLL and Frequency Synthesis PLL. R1141Q371B on stock OPERATION - READ CYCLE The DS1384 executes a read cycle whenever WE iS inactive (high) and CE and OE are active (low). The unique address specified by the address inputs (AO-A16) defines which of the on-chip 64 RTC/RAM or external SRAM locations is to be accessed. When the address value presented to the DS1384 is in the range of OOOOOH through 0003FH, one of the 64 0n-chip registers will be selected and valid data will be available to the eight data output drivers within tACC (access time) after the address input signal is stable, providing that the CE and OE access times are also satisfied. If they are not, then data access must be measured from the latter occurring signal (CE or OE) and the limiting parameter is either tco for CE or tOE for OE rather than the address access time. When one of the on-chip registers is selected for read, the OER signal will remain inactive throughout the read cycle.
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