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RS-5-3R92-1 Datasheet

This product complies with Part 68 0fthe FCC Rules and Regulations. On each device shipped, there is a label which contains, among other information, the FCC Registration Number and Ringer Equivalence Number (REN) for this product. You must, upon request, provide this information to your telephone company.
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Pin Number	Pin Name	PWR	I/O	Pin Description
11	SELSDR_DDR#/ PCI1	VDDPCI	I/O PD	Power-on Bidirectional Input/Output. At power-up, SELSDR_DDR is the input. When the power supply voltage crosses the input threshold voltage, SELSDR_DDR state is latched and this pin becomes PCI clock output. SeISDR_DDR#.= 0, DDR Mode. SeISDR_DDR#.= 1, SDR Mode.
21	FS2/24 48M	VDD48M	I/O PD	Power-on Bidirectionallnput/Output. At power-up, FS2 is the input. When the power supply voltage crosses the input threshold voltage, FS2 state is latched and this pin becomes 24_48M, a Slo programmable clock output.
6	AGPO	VDDAGP	O	AGP Clock Output. Is synchronous to CPU clocks. See Table 7
8	AGP2	VDDAGP	O	AGP Clock Output. Is synchronous to CPU clocks. See Table 7
25	IREF		I	Current reference programming input for CPU buffers. A precise resistor is attached to this pin, which is connected to the internal current reference.
28	SDATA		1/0	Serial Data Input. Conforms to the Phillips 12C specification of a Slave Receive/Transmit device. It is an input when receiving data. It is an open drain output when acknowledging or transmitting data.
27	SCLK		I	Serial Clock Input. Conforms to the Philips 12C specification.
26	PD/SRESET#		I/O PU	Power-downlnput/System Reset Control Output. If Byte6 Bit7 = O(default), this pin becomes a SRESET# open drain output. See system resetdescription. If Byte6Bit7 = 1, this pin becomes PD# input with an internal pull-up. When PD# is asserted low, the device enters power down mode. See power management function.
45	BUF IN			If SeISDR_DDR.= 0, 2.5V CMOS type input to the DDR differential buffers. If SeISDR_DDR#.= 1, 3.3V CMOS type input to the SDR buffer.
46	FBOUT			If SeISDR_DDR#.= 0, 2.5V single ended SDRAM buffered output of the signal applied at BUF_IN. It is in phase with the DDRT(0:5) signals.lf SeISDR_DDR#.= 1, 3.3V single ended SDRAM buffered output of the signal applied at BUF_IN. It is in phase with the SDRAM(O:11) signals
5	VDDAGP			3.3V power supply for AGP clocks
51	VDDC			3.3V power supply for CPUT/C clocks
16	VDDPCI			3.3V power supply for PCI clocks
55	VDDR			3.3V power supply for REF clock
50	VDDI			2.5V power supply for CPUCS_T/C clocks
22	VDD 48M			3.3V power supply for 48M
23	VDD			3.3V Common power supply
34,40	VDDD			If SeISDR_DDR#.= 0, 2.5V power supply for DDR clockslf SeISDR_DDR#.= 1, 3.3V power supply for SDR clocks.
9	VSSAGP			Ground for AGP clocks
13	VSSPCI			Ground for PCI clocks
54	VSSC			Ground for CPUT/C clocks
33,39	VSSD			Ground for DDR clocks
19	VSS 48M			Ground for 48M clock
47	VSSI			Ground forICPUCS_T/C clocks
2	VSSR			Ground for REF
24	VSS			Common Ground

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Parameter	Description	Test Conditions	TQFP Package	BGA Package	Unit
CIN	Input Capacitance	TA = 250C, f = 1 MHz,	5	5	pF
CCLK	Clock Input Capacitance	VDD = 3.3V. VDDQ = 3.3V	5	5	pF
Cl/0	Input/Output Capacitance	VDD = 3.3V. VDDQ = 3.3V	5	7	pF

Dimensions	Inches	Mimeters
L	O87	22.0
M	O33	8 5
N	O10	2 5
D	0.85	21.5
Q	O98	25.0
R	O11	2 8
S	M6	M6
T	0.26 Dia.	6.5 Dia.
U	O02	0 5
V	0.62	15.85

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