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RS560C Datasheet

Parameter	Symbol	Min	Typ	Max	Unit
Program Time	tPROG		O25	1.5	ms
Number of Partial Program Cycles in the Same Page	Nop			10	cycles
Block Erase Time	tBERS		2	10	ms

RS560C Price

PARAMETER	SYMBOL	FIGURE	MIN	TYP	MAX	UNITS
DYNAMIC SPECIFICATIONS
CLK ENC, CLK DEC Input Frequency	fCL				8 5	MHz
CLK ENC,CLK DEC Rise Time (1.544MHz)	tRCL	1.2		10	60	ns
Fall Time	tFCL	1.2		10	60	ns
Rise Time (2.048MHz)	tRCL	1.2		10	40	ns
Fall Time	tFCL	1.2		10	40	ns
Rise Time (6.3212MHz)	tRCL	1.2		10	30	ns
Fall Time	tFCL	1.2		10	30	ns
Rise Time (8.448MHz)	tRCL	1.2		5	10	ns
Fall Time	tFCL	1.2		5	10	ns

RS560C on stock

The X and Y registers are used to address any 4-bit item in the RAM. A fetch operation moves the addressed nibble onto the TOS. A store operation moves the TOS to the addressed RAM location. By using either the pre-increment or post-decrement address- ing mode arrays in the RAM can be compared, filled or moved.

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