| Part Numbert | Mfg | Packt | D/C | Descriptiont | Qty | Company/Contact |
RSB6.8SGTE61 Datasheet
RSB6.8SGTE61 Price The Hewlett Packard Deskjet 660C was initially introducad in 1995 and achieves a resolution of 600 x 600 dpi in black mode and 300 x 300 dpi in graphic,mode due to the HP Resolution Enhancement Technology (Ret). This printer's target group is the professional user who is in- terested in extremely sharp black images and brilliant and bright colours. RSB6.8SGTE61 on stock The AS Series of Arrester blocks is primarily designed to be used as the surge suppression element within a lightning arrester assembly. These arrester blocks provide the high peak surge current and energy ratings required for the protection of high voltage AC power utility distribution systems. Typically, these devices are placed within a special arrester housing provided by the customer, and stacked to achieve the necessary continuous working voltage ratings for the specific application. (See the CA or NA series of Varistor discs for lower voltage and energy applications.) [1] D = guaranteed by design; c = guaranteed by characterization; I = 100 % industrially tested. [2] The circuit has two clock inputs: CLK and CLKN. There are 5 modes of operation: a) PECL mode l: (DC levels vary l:1 with VCCD) CLK and CLKN inputs are at differential PECL levels. b) PECL mode 2: (DC levels vary l:1 with VCCD) CLK input is at PECL level and sampling is taken on the falling edge of the clock input signal. A DC level of 3.65 V has to be applied on CLKN decoupled to GND via a 100 nF capacitor. c) PECL mode 3: (DC levels vary l:1 with VCCD) CLKN input is at PECL level and sampling is taken on the rising edge of the clock input signal. A DC level of 3.65 V has to be applied on CLK decoupled to GND via a 100 nF capacitor. d) Differential AC driving mode 4: When driving the CLK input directly and with any AC signal of minimum l V (p-p) and with a DC level of 2.5 V, the sampling takes place at the falling edge of the clock signal. When driving the CLKN input with the same signal, sampling takes place at the rising edge of the clock signal. It is recommended to decouple the CLKN or CLK input to DGND via a 100 nF capacitor. e) TTL mode 5: CLK input is at TTL level and sampling is taken on the falling edge of the clock input signal. In that case CLKN pin has to be connected to the ground. [3] The ADC input range can be adjusted with an external reference connected to FSIN pin. This voltage has to be referenced to VCCA. [4] Output data acquisition: the output data is available after the maximum delay of td(o). [5] The -3 dB analog bandwidth is determined by the 3 dB reduction in the reconstructed output, the input being a full-scale sine wave. [6] The total harmonic distortion is obtained with the addition of the first five harmonics. [7] The signal-to-noise ratio takes into account all harmonics above five and noise up to Nyquist frequency. |
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