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RSBEC3330DQ00M Datasheet

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RSBEC3330DQ00M Price

				CA3018			CA3018A
PARAMETER	SYMBOL	TEST CONDITIONS		MIN	TYP	MAX	MIN	TYP	MAX	UNITS
DC CHARACTERISTICS
Collector Cutoff Current (Figure l)	ICBO	VCB = 10V, IE = 0			0 002	100		0 002	40	nA
Collector Cutoff Current (Figure 2)	ICEO	VCE = 10V, lB = 0			See Fig.2	5		See Fig.2	0.5	A
Collector Cutoff Current Darlington Pair	ICEOD	VCE = 10V, lB = 0							5
Collector-to-Emitter Breakdown Voltage	V(BR)CEO	lc = 1mA, lB = 0		15	24		15	24		V
Collector-to-Base Breakdown Voltage	V(BR)CBO	lc = 10ccA, IE = 0		20	60		30	60		V
Emitter-to-Base Breakdown Voltage	V(BR)EBO	IE = 100:A, lc = 0		5	7		5	7		V
Collector-to-Substrate Breakdown Voltage	V(BR)CIO	lc = 10GCA, lCl = 0		20	60		40	60		V
Collector-to-Emitter Saturation Voltage	VCES	lB = 1mA, lc = 10mA			0 23			0 23	0.5	V
Forward Current Transfer Ratio (Note 3)	hFE	VCE= 3V	lc= 10mA		100		50	100
(Figure 3)			lc= 1mA	30	100	200	60	100	200
(Figure 3)			lc= 10ccA		54		30	54
Magnitude of Static-Beta Ratio (Isolated Transistors Ql and Q2) (Figure 3)		VCE = 3V, lcl = lC2 = 1mA		0.9	0 97		0.9	0 97
Forward Current Transfer Ratio Darling-	hFED	VCE= 3V	lc= 1mA	1500	5400		2000	5400
ton Pair (Q3 and Q4) (Figure 4)	hFED	VCE= 3V	lc= 100ccA				1000	2800
Base-to-Emitter Voltage (Figure 5)	VBE	VCE= 3V	IE= 1mA		0 715		0 600	0 715	0 800	V
Base-to-Emitter Voltage (Figure 5)	VBE	VCE= 3V	IE= 10mA		0 800			0 800	0 900	V
Input Offset Voltage (Figures 5, 7)	VBE11 l-VBE21	VCE = 3V, IE = 1mA			0 48	5		0 48	2	mV
Temperatu re Coeicient: Base-to-Emitter Voltage Ql, Q2 (Figure 6)	l~/BEI	VCE = 3V, IE = 1mA			-1.9			-1.9		mVPC

RSBEC3330DQ00M on stock

INPUTS				OUTPUTS
VDD> VLL	VDD> VIT	VDD> VBAT	MSWITCH	VOUT	BATTON	LOWLINE	RESET	CEOUT
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1	0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1	0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1	0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1	VBAT VBAT VBAT VBAT VDD VDD VBAT VBAT VDD VDD VBAT VBAT VDD VDD VBAT VBAT VDD VDD VBAT VBAT VDD VDD VBAT VBAT	1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1	0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1	0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1	DIS DIS DIS DIS DIS DIS DIS DIS DIS EN DIS EN DIS EN DIS EN DIS EN DIS EN DIS EN DIS EN

The STi3520Ais similar to the STi3520 audioNideo decoder but with a memory optimsation function, an audio bit-butfer integrated in DRAM, an en- hanced PLL, an additionaIOSD mode and a PES parser. The memory optimisation function allows PAL decoding with OSD in 16Mbas of DRAM. The PLL allows full circuit operation using only one extemaldock (eg a system dock of 27MHz). The OSD has a new mode (4 bits/2 pixels), this allows a fullscreen, 16 color OSD for PAL operation in 16 MBits of memory.The STi3520A can accept pack- etised elementary stream (PES) data as defined in the International Standard ISO/IEC 13818-1 (MPEG2 )and ISO/IEC 11172-1 (MPEG-1). The microcontrollerinterface has an 8-bit data bus and a 7-bit address bus. This access port has two functions : - to pass the compressed data to the audio and video decoders, - to enable control of the STi3520A by providing interrupts and a path for accessing internal regis- ters.

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