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RSE2-2-10-SG-1 Datasheet FEATURES: , Input frequency: - For SONETnon-FEC:19.44MHz,38.88MHz, 77.76MHz, 155.52MHz, 311.04MHz, or 622.08MHz - For SONET FEC: 20.83MHz, 41.66MHz, 83.31MHz, 166.63MHz, 333.26MHz, or 666.52MHz - For 10GE copper: 19.53MHz, 39.06MHz, 78.125MHz, 156.25MHz, 312.5MHz, or 625MHz - For 10GE optical: 20.14MHz, 40.28MHz, 80.56MHz, 161.13MHz, 322.26MHz, or 644.53MHz . 3-levelinputs forfeedback divide ratio and outputfrequency range selection * 1x, 2x, 4x, 8x, 16x, and 32x outputs on QOUT . Regenerated input clock or QOUT/4 0n QREG . Lock indicator . Power-down mode . LVPECL or LVDS outputs . Three modes of output frequency range - Mode 0: QOUTrange 755.5 - 166.6MHz. QREG is a regenerated version of the input clock. - Mode 7: QOUTrange 622 - 666.5MHz. QREG output155.5-166.6MHz. - Mode 2: QOUTrange 622 - 666.5MHz. QREG is a regenerated version of the input clock frequency. . Selectable loop bandwidths . Hitless switchover . Differential LVPECL, LVDS, or single-ended LVTTLinput interface . 2.375 - 3.465V core and l/0 . Available in VFQFPN package RSE2-2-10-SG-1 Price
RSE2-2-10-SG-1 on stock A second on-chip PLL generates a selectable multiple of the sample rate frequency supplied on the word select pin IIS_WS (= IIS_WSl). The clock generated by this so called WS_PLL is available for the user at pin SYSCLK. Tables 3 and 4 show the I2C_bus settings needed to generate the n x fs clock. The memory map of the I2C_bus bits is shown in Table 10.
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