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This device is a 264Mbit(276,824,064 bit) memory organized as 65,536 rows(pages) by 528 columns. Spare eight columns are located from column address of 512~527. A 528-byte data register is connected to memory cell arrays accommodating data transfer between the l/0 buffers and memory during page read and page program operations. The memory array is made up of 16 cells that are serially connected to form a NAND structure. Each of the 16 cells resides in a different page. A block consists of two NAND struc- tured strings. A NAND structure consists of 16 cells. Total 135168 NAND cells reside in a block. The array organization is shown in Figurel. The program and read operations are executed on a page basis, while the erase operation is executed on a block basis. The memory array consists of 2048 separately erasable 16K-Byte blocks. It indicates that the bit by bit erase operation is prohibited on this device. This device has addresses multiplexed int0 8 l/O's. This device allows sixteen bit wide data transport into and out of page registers. This scheme dramatically reduces pin counts while providing high performance and allows systems upgrades to future densities by maintaining consistency in system board design. Command, address and data are all written through llO's by bringing WE to low while CE is low. Data is latched on the rising edge of WE. Command Latch Enable(CLE) and Address Latch Enable(ALE) are used to multiplex command and address respectively, via the l/0 pins. Some commands require one bus cycle. For example, Reset com- mand, Read command, Status Read command, etc require just one cycle bus. Some other commands like Page Program and Copy- back Program and Block Erase, require two cycles: one cycle for setup and the other cycle for execution. The 32M-byte physical space requires 24 addresses, thereby requiring three cycles for word-level addressing: column address, low row address and high row address, in that order. Page Read and Page Program need the same three address cycles following the required command input. In Block Erase operation, however, only the two row address cycles are used. Device operations are selected by writing spe- cific commands into the command register. Table l defines the specific commands of this device. The device includes one block sized OTP(One Time Programmable), which can be used to increase system security or to provide identification capabilities. Detailed information can be obtained by contact with Samsung.
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