To minimize the coupling of unwanted noise into the receiver, route high-level, high-speed signals such as transmitter inputs and clock lines as far away as possi- ble from the receiver pins. If this is not possible, then the PWB layout engineer should consider interleaving the receiver signal and flag traces with ground traces in order to provide the required isolation.
RT0402BRD074K75L Price| 47.5 23 1 23 k I / MntIoq'o'. 12 12 it rri rri rn |
| | | | E{* | | | |
| | | | | I |
| l, l ' IBI :Z 1' | lj ' f |
| Tab WP* tarminak 3-M5 (AMP No.ll0 *quivaknt) |
| n | n{jr | |
| j | Ll | |
| f | |
| CASE | M209 |
| UL | E82988(M) |
| | | | | | | | |
RT0402BRD074K75L on stock| l Class lcatlon | O | Y | G |
| I h | 70-140 | 120-240 | 200-400 |
| | | |
@ 2000 STMicroelectronics - Printed in Italy - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - B razil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A.
