| PARAMETER | TEST CONDITIONS | MIN TYP MAX | UNIT |
| VID(2) Differential input sensitivityt | | 150 1560 | mVp_p |
| tps Analog input intra-pair (+ to -) differential skew (see Note 6) | | 0.4 | tbitt |
| Analog Input inter-pair or channel-to-channel skew tccs (see Note 6) | | 1 | tpix§ |
| Worse case differential input clock jitter tolerancell tijit (see Note 6) | | 50 | ps |
| tfl Fall time of data and control signals#, lI | ST = Low, CL=5 pF ST = High, CL=10 pF | 2.4 1.9 | ns |
| trl Rise time of data and control signals#, lI | ST = Low, CL=5 pF ST = High, CL=10 pF | 2.4 1.9 | ns |
| tr2 Rise time of ODCK clock# | ST = Low, CL=5 pF ST = High, CL=10 pF | 2.4 1.9 | ns |
| tf2 Fall time of ODCK clock# | ST = Low, CL=5 pF ST = High, CL=10 pF | 2.4 1.9 | ns |
| Setup time, data and control signal to falling edge of ODCK tsul (OCK_INV = low)ll | ST = Low, CL=5 pF ST = High, CL=10 pF | 2 3 | ns |
| Hold time, data and control signal to falling edge of ODCK thl (OCK_INV = low)ll | ST = Low, CL=5 pF ST = High, CL=10 pF | 2 3 | ns |
| Setup time, data and control signal to rising edge of ODCK tsu2 (OCK_INV = high)ll | ST = Low, CL=5 pF ST = High, CL=10 pF | 2 3 | ns |
| Hold time, data and control signal to rising edge of ODCK th2 (OCK_INV = high)ll | ST = Low, CL=5 pF ST = High, CL=10 pF | 1 8 | ns |
| | PIX = Low (1-PIX/CLK) | 25 112 | |
| fODCK ODCK frequency | PIX = High (2-PIX/CLK) | 12 5 56 | MHz |
| ODCK duty-cycle | | 40% 50% 60% | |
| tpd(PDL) Propagation delay time from PD low to Hi-Z outputs | | 9 | ns |
| tpd(PDOL) Propagation delay time from PDO low to Hi-Z outputs | | 9 | ns |
| tt(HSC) Transition time between DE transition to SCDT lowik | | 1e6 | tpix |
| tt(FSC) Transition time between DE transition to SCDT high* | | 1600 | tpix |
| td(st) Delay time, ODCK latching edge to QE[23:0] data output | STAG = Low Pixs = High | 0.25 | tpix |
| | | |
Stock Conditions +lOoC to +600C relative humidit\/ " 75% yearly average, without dew, maximum value for 30 days-95% Vibration Resistance 24 cycles at 15 min. each (EN 60068-6) 10 - 60Hz at 0.75mm amplitude 60 - 2000Hz at 10g acceleration Lead Pull Strength 10N (EN 60068-2-21) S old e ra bility 2600C, " 3 sec. (Wave) 3500C, " 1 sec. (Hand)
RT086AENG-4 on stock| RATINGS | SYMBOL | 1N17 | 1N18 | 1N19 | U NITS |
| Maximum Recurrent Peak Reverse Voltage | VRRM | 20 | 30 | 40 | Volts |
| Maximum RMS Voltage | VRMS | 14 | 21 | 28 | Volts |
| Maximum DC Blocking Voltage | VDC | 20 | 30 | 40 | Volts |
| Maximum Average Forward Rectified Current 375" [9 5mm) lead length at TL = 900C | IO | 1 0 | Amps |
| Peak Forward Surge Current 8.3 ms single half sine-wave superimposed on rated load (JEDEC method) | | 20 | Amps |
| Typical Thermal Resistance (Note l) | ROJA | 80 | oc/w |
| Typical Junction Capacitance (Note 2) | cJ | 110 | pF |
| Storage and Operating Temperature Range | TJ, TSTG | -65 to +150 | oc |
| | | | | |
These devices feature the ability to clamp dangerous high voltage short term transients such as produced by directed or radiated electro-static-discharge phenomena before entering sensitive component regions of a circuit desig n. They are small economicaltransient voltage suppressors targeted primarily for short term transients below a few microseconds while still achieving significant peak-pulse-power capability as seen in Figure #1.
