RT1N431C-T112，there are the best RT1N431C-T112 suppiers all over the world here.These are the list and detailed contact method of RT1N431C-T112 suppliers all over the world as follows.You can buy or get informations of RT1N431C-T112 through email , message or tel.

suppliers of RT1N431C-T112 and PDF data of RT1N431C-T112

Part Numbert

Mfg

Packt

D/C

Descriptiont

Qty

Company/Contact

RT1N431C-T112 Datasheet

Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
RT1N431C-T112 on stock

		Test Condition		Va		ue
Symbol	Parameter			-40 t0 85 0C		-55 t0 125 0C		Unit
Symbol	Parameter	vcc (v)		Min	Max	Min	Max	Unit
VIH	High Level Input	1.65 t0 1.95		1.32		1.32		V
	Voltage	2.3		1.84		1.84
		2.7		2.16		2.16
		3.0		2.40		2.40
		3.6		2.88		2.88
VIL	Low Level Input	1.65 t0 1.95			0.4		0.4	V
	Voltage	2.3			0.5		0.5
	Voltage	2.7 t0 3.6			0.65		0.65
VOH	High Level Output	1.65 t0 3.6	lo=-100A	Vcc-0.2		Vcc-0.2		V
	Voltage	1.65	lo=-4 mA	1.2		1.2
		2.3	lo=-8 mA	1.7		1.7
		2.7	lo=-12 mA	2.2		2.2
		3.0	lo=-18 mA	2.4		2.4
		3.0	lo=-24 mA	2.2		2.2
VOL	Low Level Output	1.65 t0 3.6	10=100cA		0.2		0.2	V
	Voltage	1.65	10=4 mA		0.45		0.45
		2.3	10=8 mA		0.7		0.7
		2.7	10=12 mA		0.4		0.4
		3.0	10=24 mA		0.55		0.55
l J	Input Leakage Current	3.6	VI=0 t0 5.5V		±5		±5	cA
loff	Power Off Leakage Current	0	Vi or Vo = 5.5V		10		10	cA
lcc	Quiescent Supply		Vl = Vcc or GND		10		10
lcc	Current	3.6	Vi or Vo = 3.6 to 5.5V		±10		±10	cA
Clcc	lcc incr. per Input	2.7 t0 3.6	VIH = Vcc-0.6V		500		500

Parameter	Temp	Test Level	Min Typ Max	Unit
CLK TIMING REQUIREMENTS tCLK CLKx Period (x = A, B, C, D) tCLKL CLKx Width Low (x = A, B, C, D) tCLKH CLKx Width High (x = A, B, C, D) tCLKSKEW CLKA to CLKx Skew (x = B, C, D)	Full F ull Full Full	l IV IV IV	6.66 1.71 0.5 x tCLK 1.70 0.5 x tCLK tCLK - 1.3	ns ns ns ns
INPUT WIDEBAND DATA TIMING REQUIREMENTS tsi INx [1 5:0] to TCLKx Setup Time (x = A, B, C, D) tHI INx [1 5:0] to TCLKx Hold Time (x = A, B, C, D) tSEXP EXPx [2:0] to TCLKx Setup Time (x = A, B, C, D) tHEXP EXPx [2:0] to TCLKx Hold Time (x = A, B, C, D) tDEXP TCLKx to EXPx[2:0] Delay (x = A, B, C, D)	F ull F ull F ull Full Full Full	IV IV IV IV IV IV	0.75 1.1 3 3.37 1 .11 5.98 10.74	ns ns ns ns ns
PARALLEL OUTPUT PORT TIMING REQUIREMENTS (MASTER) tDPREQ TPCLK to TPx REQ Delay (x = A, B, C) tDPP TPCLK to Px [15:0] Delay (x = A, B, C) tDPIQ TPCLK to Px io Delay (x = A, B, C) tDPCH TPCLK to Px CH[2:0] Delay (x = A, B, C) tDPGAIN TPCLK to Px Gain Delay (x = A, B, C) tSPA Px ACK to TPCLK Setup Time (x = A, B, C) tHPA Px ACK to TPCLK Hold Time (x = A, B, C)	F ull Full Full Full Full Full Full	IV IV IV IV IV IV IV	1.77 3.86 2.07 5.29 0.48 5.49 0.38 5.35 0.23 4.95 4.59 0.90	ns ns ns ns ns ns ns
PARALLEL OUTPUT PORT TIMING REQUIREMENTS (SLAVE) tPCLK PCLK Period tPCLKL PCLK Low Period tPCLKH PCLK High Period tDPREQ TPCLK to TPx REQ Delay (x = A, B, C) tDPP TPCLK to Px [1 5:0] Delay (x = A, B, C) tDPIQ TPCLK to Px io Delay (x = A, B, C) tDPCH TPCLK to Px CH[2:0] Delay (x = A, B, C) tDPGAIN TPCLK to Px Gain Delay (x = A, B, C) tSPA Px ACK t0 1PCLK Setup Time (x = A, B, C) tHPA Px ACK t0 1PCLK Hold Time (x = A, B, C)	F ull F ull F ull F ull Full Full Full Full Full Full	IV IV IV IV IV IV IV IV IV IV	5.0 1.7 0.5 x tPCLK 0.7 0.5 x tPCLK 4.72 8.87 4.8 8.48 4.83 10.94 4.88 10.09 5.08 11.49 6.09 1.0	ns ns ns ns ns ns ns ns ns ns
MISC PINS TIMING REQUIREMENTS tRE5ET RESET Width Low tDIRP CPUCLK/SCLK to ~RP Delay tss SYNC(O, 1, 2, 3) to TCLKA Setup Time tHS SYNC(O, 1, 2, 3) to TCLKA Hold Time	F ull F ull F ull F ull	IV V IV IV	30 7.5 0.87 0.67	ns ns ns ns

Suppliers Datasheet
		Exact Matc