The Host Interface has been designed to be flexible enough to allowits use from small microprocessorsystems to PC-Card slots. In a minimum configuration it uses only 4 address locations and a standard microprocessor type read and write cycle. The interface provides access to the Buffer RAM, which is accessible by both the Host and the MAC systems simultaneously, and also to a control regis- ter which allows the Host to reset or interrupt the MAC processor, and performs some other control functions on the WL102.
RT22C2W202 on stock| | | TEST CONDITION | Ta= 250C | Ta = - 40850C | |
| CHARACTERISTIC | SYMBOL | | VCC (V) | CL (pF) | MIN | TYP | MAX | MIN | MAX | UNIT |
| | | | 3.3±0.3 | 1 5 | | 5.6 | 8.0 | 1.0 | 9.5 | |
| Propagation Delay | tpLH | 50 | | 8.1 | 11.5 | 1.0 | 13.0 |
| | 1 5 | | 3.8 | 5.5 | 1.0 | 6.5 | ns |
| Time | tpHL | 5O±0.5 | 50 | | 5.3 | 7.5 | 1.0 | 8.5 |
| | | | | 1 5 | | 5.4 | 8.0 | 1.0 | 9.5 | |
| 3-State Output | tpZL | RL= lk(l, | 3.3±0.3 | 50 | | 7.9 | 11.5 | 1.0 | 13.0 |
| | 1 5 | | 3.6 | 5.1 | 1.0 | 6.0 | ns |
| Enable Time | tpZH | 5O±0.5 | 50 | | 5.1 | 7.1 | 1.0 | 8.0 |
| 3-State Output | tpLZ | RL=lkfl | 3.3±0.3 | 50 | | 9.5 | 13.2 | 1.0 | 15.0 | |
| Disable Time | toHZ | 5.0±0.5 | 50 | | 6.1 | 8.8 | 1.0 | 10.0 | ns |
| Output to Output | tosLH | (Note l) | 3.3±0.3 | 50 | | | 1.5 | | 1.5 | |
| Skew | tosHL | 5O±0.5 | 50 | | | 1.0 | | 1O | ns |
| Input Capacitance | CIN | | | 4 | 10 | | 10 | pF |
| Output Capacitance | COUT | | | 6 | | | | pF |
| Power Dissipation Capacitance (Note 2) | CPD | | | 14 | | | | pF |
| | | | | | | | | | |
| Type | VDS | ID | RDS(on) | Package | Ordering Code |
| BUZ 10 | 50 V | 23 A | 0.07 l | T0-220 AB | C67078-S1300-A2 |
| | | | | |
