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High to Low at DOUT pin is within the time which 9 t0 15 waves to pass. In this case, one wave is referenced t0 16 Fosc clocks. The time width is determined by the internal clock and amplifier input signal. The timings of the internal clock and internal detection signal in the majority logic circuit are synchronous with each other. When input signals with the cycle, which is within the range specified by the frequency window, are detected (or not detected) sequentially, this rule is valid (the majority rule).