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RT9161A36CZT Datasheet

SYmbO Parameter Conditions Ratings U nit
VRRM Repetitive peak reverse voltage 600 V
VR SM Non-repetitive peak reverse voltage 720 V
VR lDC) DC reverse voltage 480 V
IDC DC current DC circuit, resistive, inductive load 30 A
IFSM Surge {non-repetitive) forward current Peak value of one c\cle of 60Hz (half wavel 600 A
12t h for fusing Value for one c\icle of surge current 1 5×100 A2S


RT9161A36CZT Price

TYPE VDSS RDS(on) IOUT vcc
VND05BSP 40 V 0.2 l 1.6 A 26 V


RT9161A36CZT on stock
XPLATM ARCHITECTURE Figure l shows a high level block diagram of a 64 macrocell device implementing the XPLATM architecture. The XPLATM architecture consists of logic blocks that are interconnected by a Zero-power Interconnect Array (ZIA). The ZIA is a virtual crosspoint switch. Each logic block is essentially a 36V16 device with 36 inputs from the ZIA and 16 macrocells. Each logic block also provides 32 ZIA feedback paths from the macrocells and l/0 pins.

PERATE POl qJT
VCC=14V
RELEAS E POINT