| Symbol | Parameter | Mln | Max | Unlts | Test Condltlons |
| tCP | Port Control Setup before Falling Edge of PROG | 10 | | ns | |
| tPC | Port Control Hold after Falling Edge of PROG | 100 | | ns | |
| tPR | PROG to Time P2 Input Must Be Valid | | 810 | ns | |
| tPF | Input Data Hold Time | 0 | 150 | ns | |
| tDP | Output Data Setup Time | 250 | | ns | |
| tPD | Output Data Hold Time | 65 | | ns | |
| tPP | PROG Pulse Width | 1200 | | ns | |
| | | | | |
at the next address can be read sequentially by continuing to provide clock pulses. The address is automatically incremented to the next higher address after each byte of data is shifted out. When the highest address is reached ($3FFF) the address counter rolls over to address $0000 allowing the read cycle to be continued indefinitely. The read operation is termi- nated by taking CS HIGH. Refer to the read E2PROM array operation sequence illustrated in Figure l.
