| A50 | READ (RDN = Low) | WRITE (WRN = Low) |
| 000000 | Mode Register a (MROa, MRla, MR2a) | Mode Register a (MROa, MRla, MR2a) |
| 000001 | Status Register a (SRa) | Clock Select Register a (CSRa) |
| 000010 | Reserved | Command Register a (CRa) |
| 000011 | Receive Holding Register a (RxFIFOa) | Transmit Holding Register a (TxFIFOa) |
| 000100 | Input Port Change Reg ab (IPCRab) | Auxiliary Control Reg ab (ACRab) |
| 000101 | Interrupt Status Reg ab (ISRab) | Interrupt Mask Reg ab (IMRab) |
| 000110 | Counter/Timer Upper ab (CTUab) | Counter/Timer Upper Reg ab (CTURab) |
| 000111 | Counter/Timer Lower ab (CTLab) | Counter/Timer Lower Reg ab (CTLRab) |
| 001000 | Mode Register b (MROb, MRlb, MR2b) | Mode Register b (MROb, MRlb, MR2b) |
| 001001 | Status Register b (SRb) | Clock Select Register b (CSRb) |
| 001010 | Reserved | Command Register b (CRb) |
| 001011 | Receive Holding Register b (RxFIFOb) | Transmit Holding Register b (TxFIFOb) |
| 001100 | Output Port Register ab (OPRab) | Output Port Register ab (OPRab) |
| 001101 | Input Port Register ab (IPRab) | l/OPCRa (l/0 Port Control Reg a) |
| 001110 | Start Counter ab | l/OPCRb (l/0 Port Control Reg b) |
| 001111 | Stop Counter ab | Reserved |
| 010000 | Mode Register c (MROc, MRlc, MR2c) | Mode Register c (MROc, MRlc, MR2c) |
| 010001 | Status Register c (SRc) | Clock Select Register c (CSRc) |
| 010010 | Reserved | Command Register c (CRc) |
| 010011 | Receive Holding Register c (RxFIFOc) | Transmit Holding Register c (TxFIFOc) |
| 010100 | Input Port Change Reg cd (IPCRcd) | Auxiliary Control Reg cd (ACRcd) |
| 010101 | Interrupt Status Reg cd (ISRcd) | Interrupt Mask Reg cd (IMRcd) |
| 010110 | Counter/Timer Upper cd (CTUcd) | Counter/Timer Upper Reg cd (CTURcd) |
| 010111 | Counter/Timer Lower cd (CTLcd) | Counter/Timer Lower Reg cd (CTLRcd) |
| 011000 | Mode Register d (MROd, MRld, MR2d) | Mode Register d (MROd, MRld, MR2d) |
| 011001 | Status Register d (SRd) | Clock Select Register d (CSRd) |
| 011010 | Reserved | Command Register d (CRd) |
| 011011 | Receive Holding Register d (RxFIFOd) | Transmit Holding Register d (TxFIFOd) |
| 011100 | Output Port Register cd (OPRcd) | Output Port Register cd (OPRcd) |
| 011101 | Input Port Register cd (IPRcd) | l/OPCRc (l/0 Port Control Reg c) |
| 011110 | Start Counter cd | l/OPCRd (l/0 Port Control Reg d) |
| 011111 | Stop Counter cd | Reserved |
| 100000 | Bidding Control Register a (BCRa) | Bidding Control Register a (BCRa) |
| 100001 | Bidding Control Register b (BCRb) | Bidding Control Register b (BCRb) |
| 100010 | Bidding Control Register c (BCRc) | Bidding Control Register c (BCRc) |
| 100011 | Bidding Control Register d (BCRd) | Bidding Control Register d (BCRd) |
| 100100 | Reserved | Power Down |
| 100101 | Reserved | Power Up |
| 100110 | Reserved | Disable DACKN |
| 100111 | Reserved | Enable DACKN |
| 101000 | Current Interrupt Register (CIR) | Reserved |
| 101001 | Global Interrupting Channel Reg (GICR) | Interrupt Vector Register (IVR) |
| 101010 | Globallnt Byte Count Reg (GIBCR) | Update CIR |
| 101011 | Global Receive Holding Reg (GRxFIFO) | Global Transmit Holding Reg (GTxFIFO) |
| 101100 | Interrupt Control Register (ICR) | Interrupt Control Register (ICR) |
| 101101 | Reserved | BRG Rate. 00 = low; 01 = high |
| 101110 | Reserved | Set Xl/CLK divide by twoz |
| 101111 | Reserved | Set Xl/CLK Normalz |
| 110000-111000 | Reserved | Reserved |
| 111001 | Test Mode | Test Mode |
| 111010-111111 | Reserved | Reserved |
| | |
