| Parameter | 10RIA | U nits | Conditions |
| IT(AV) Max. average on-state current | 10 | A | 1800 conduction, half sine wave |
| @ Case temperature | 85 | oc |
| IT(RMS) Max. RMS on-state current | 25 | A | |
| ITSM Max. peak, one-cycle | 225 | A | t= 10ms | No voltage | |
| non-repetitive surge current | 240 | t= 8.3ms | reapplied |
| 190 | t= 10ms | 100% VRRM |
| 200 | t= 8.3ms | reapplied | Sinusoidal half wave, |
| 12t Maximum l2t for fusing | 255 | | t= 10ms | No voltage | Initial Tj = Tj max. |
| 233 | A2S | t= 8.3ms | reapplied |
| 180 | t= 10ms | 100% VRRM |
| 165 | t= 8.3ms | reapplied |
| 12 ft Maximum l2 th for fusing | 2550 | A2 | t = 0.1 t0 10ms, no voltage reapplied |
| VT(TO)1 Low level value of threshold voltage | 1 10 | V | (16.7% x # x IT(AV) < I < * X IT(AV, Tj = Tj max. |
| VT(T0)2 High level value of threshold voltage | 1 39 | (l > *x IT(AV' Tj = Tj max. |
| rti Low level value of on-state slope resistance | 24 3 | ml | (16.7% x # x IT(AV) < I < * X IT(AV, Tj = Tj max. |
| rt2 High level value of on-state slope resistance | 16 7 | (l > *x IT(AV, Tj = Tj max. |
| VTM Max. on-state voltage | 1 75 | V | pk= 32A, Tj = 250C tp = 10ms sine pulse |
| IH Maximum holding current | 130 | | |
| IL Typical latching current | 200 | mA | Tj = 250C, anode supply 12V resistive load |
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= 111, then all 4 bits are high. If TECH[2:0] = 001, then only bit 5 is high. After reset, software can change any of these bits from a l to a 0; but not from a o to a l. Therefore, a technology permitted by the setting of the TECH pins can be disabled, but one not permitted cannot be enabled.
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