| PIN | PIN NAME | DESCRIPTION |
| CLK | Clock | The system clock input. All other inputs are registered to the SDRAM on the rising edge of CLK |
| CKE | Clock Enable | Controls internal clock signal and when deactivated, the SDRAM will be one of the states among power down, suspend or self refresh |
| cs | Chip Select | Enables or disables all inputs except CLK, CKE and DQM |
| BAO, BA1 | BankAddress | Selects bank to be activated during RAS activity Selects bank to be read/written during CAS activity |
| AOA11 | Address | Row Address : RAO ~ RA11, Column Address : CAO ~ CA9 Auto-precharge flag : A10 |
| RAS, CAS, WE | Row Address Strobe, Col- umn Address Strobe, Write Enable | RAS, CAS and WE define the operation Refer function truth table for details |
| DQM | Data Input/Output Mask | Controls output buffers in read mode and masks input data in write mode |
| DQODQ7 | Data Input/Output | M ultiplexed data input / output pin |
| VDDNSS | Power Supply/Ground | Power supply for internal circuits and input buffers |
| VDDQ/VSSQ | Data Output Power/Ground | Power supply for output buffers |
| NC | No Connection | No connection |
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