| Part Numbert | Mfg | Packt | D/C | Descriptiont | Qty | Company/Contact |
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SKN7-S Datasheet The A63P83361 is a high-speed SRAM containing 9M bits of bit synchronous memory, organized as 256K words by 36 bits. The A63P83361 combines advanced synchronous peripheral circuitry, 2-bit burst control, input registers, output buffer and a 256K X 36 SRAM core to provide a wide range of data RAM applications. The positive edge triggered single clock input (CLK) controls all synchronous inputs passing through the registers. Synchronous inputs include all addresses (AO - A17), all data inputs (l/0i - l/036 ), active LOW chip enable (CE ), two additional chip enables (CE2, CE2 ), burst control inputs ( ADSC , ADSP , ADV ), byte write enables ( BWE , BWl, BW2 , BW3, BW4 ) and Global Write ( GW ). Asynchronous inputs include output enable (OE ), clock (CLK), BURST mode (MODE) and SLEEP mode (ZZ). SKN7-S Price
SKN7-S on stock Maximum Power Dissipation The power dissipated in the package (PD) iS the sum of the quiescent power dissipation and the power dissipated in the package due to the load drive for all outputs. The quiescent power is the voltage between the supply pins (Vs) times the quiescent current (Is).Assuming that the load (RL) is midsupply the total drive power is Vs/2 x Iour, some of which is dissipated in the package and some in the load (Vour x IOUT).
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