| Part Numbert | Mfg | Packt | D/C | Descriptiont | Qty | Company/Contact | |
| SKR2616 | semikron | semikron | dc04 | 1 |
|
||
| SKR2616 | semikron | semikron | dc04 | 1 |
|
||
| SKR2616 | semikron | dc04 |
|
||||
| SKR2616 | semikron | dc04 | INSTOCK!vpe:1/bulk | 1 |
|
||
| SKR2616 | semikron | semikron | dc04 | 1 |
|
SKR2616 Datasheet
SKR2616 Price LP and BP outputs can typically sink l mA and source 3 mA. The N/AP/HP output can typically sink l.5 mA and source 3 mA. Each output typically swings to within 1V of each supply. The inverting input of the summing op amp of the filter. This is a high impedance input, but the non-inverting input is internally tied to AGND, making INV1 behave like a summing junction (low impedance current input). Sl is a signal input pin used in the allpass filter configurations (see modes 4 and 5). The pin should be driven with a source impedance of less than l kfl. If Sl is not driven with a signal it should be tied to AGND (mid-supply). This pin activates a switch that connects one of the inputs of the filter's second summer to either AGND (SA tied to V-) or to the lowpass (LP) output (SA tied to v + ). This offers the flexibility needed for configuring the filter in its various modes of operation. This pin is used to set the internal clock to center frequency ratio (fCLK/fo) of the filter. By tying the pin to V+ an fCLK/fo ratio of about 50:1 (typically 50.11 + 0.2%) is obtained. Tying the 50/100 pin to either AGND or V- will set the fCLK/fo ratio to about 100:1 (typically 100.04 + This is the analog ground pin. This pin should be connected to the system ground for dual supply operation or biased to mid-supply for single supply operation. For a further discussion of mid-supply biasing techniques see the Applications Information (Section 3.2). For optimum filter performance a "clean" ground must be provided. SKR2616 on stock
FEATURES High-speed access times: 55, 70, 100 ns CMOS low power operation lcci=lOmA (typical)+ operating ISB2=1pA (typical)* CMOS standby Typical values are measured at Vcc=1.8V, TA=250C TTL compatible interface levels Single l.65V-2.2V Vcc power supply Fully static operation: no clock or refresh required Three state outputs Data control for upper and lower bytes Industrial temperature available Available in the 44-pin TSOP-2 and 48-pin 6*8mm TF-BGA |
||||||||||||||||||||||||||||||||||||||||||||||||||