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The schematic diagram to the right demon- strates the ease with which a 12-Bit Data Ac- quisition System operating at 500 KHz can be implemented using the DMC 1410 (SHA) and DMC 2851 (ADC). The positive pulse generated by the one-shot determines the length of time over which data -iS to be sampled. For .01% accuracy, pulse duration should be a minimum of 350 ns. The data is then held while the ADC makes its con- version. This technique takes maximal advan- tage of the ADC's internal logic which insures that the (SHA) has settled before making its flrst decision. Even faster data rates can be achiev- ed, if less bit resolution is acceptable. Please consuIt DMC for details.