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. A parallel-resonant crystal should be used as the reference to the clock generator. The operating frequency and CLOAD of this crystal should be as specified in the data sheet. Optional trimming capacitors may be needed if a crystal with a different CLOAD iS used. Footprints must be laid out for flexibility. Surface mount, low-ESR, ceramic capacitors should be used for filtering. Typically, these capacitors have a value of 0.1 ~F. In some cases, smaller value capacitors may be required. The value ofthe series terminating resistorsatisfies the following equation,where Rtrace is the loaded characteristic impedance ofthe trace, RoutiS the outputimpedance ofthe clockgenerator(specified in the data sheet), and Rseries is the series terminating resistor. ' Rseries > Rtrace - Rout Footprints must be laid out for optional EMI-reducing capacitors, which should be placed as close to the terminating resistor as is physically possible. Typical values of these capacitors range from 4.7 pF t0 22 pF. ' A Ferrite Bead rpay be used to isolate the Board VDD from the clock generatorVDD island. Ensure that the Ferrite Bead offers greater than sol impedance at the clock frequency, underloaded DC conditions. Please refer to the application note "Layout and Termination Techniques for Cypress Clock Generators" for more details. If a Ferrite Bead is used, a 10 ~F- 22 ~F tantalum bypass capacitorshould be placed close to the Ferrite Bead. This capacitor prevents power supply droop during current surges.
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