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suppliers of SL27J and PDF data of SL27J

Part Numbert	Mfg	Packt	D/C	Descriptiont	Qty	Company/Contact
SL27J	.	.	.		70	Liverpool (Hong Kong) Electron.. Contact:Jessica Tel:86-755-83957717 Fax: Email: info@lvphk.com
SL27J	.	.	.		70	ALLSKY(HONGKONG)ELECTRONICSCO. Contact:Jenny Jiang Tel:86-755-83014004 Fax:86-755-83014044 Email: info@allskyhk.com

SL27J Datasheet

I UPT0 3.5ASTEP DOWN CONVERTER I OPERATING INPUT VOLTAGE FROM 8V TO 55V 1 3.3V AND 5.1V (+1%) FIXED OUTPUT, AND ADJUSTABLE OUTPUTS FROM: OV T0 50V (3.3V type) 5.1VT0 50V (5.1 type) I FREQUENCYADJUSTABLE UP T0 300KHz I VOLTAGE FEED FORWARD I ZERO LOAD CURRENT OPERATION (min 1mA) I INTERNAL CURRENT LIMITING (PULSE BY PULSEAND HICCUP MODE) I PRECISE 5.1V (1.5%) REFERENCE VOLT- AGE EXTERNALLY AVAILABLE I INPUT/OUTPUT SYNCHRONIZATION FUNC- TION I INHIBIT FOR ZERO CURRENT CONSUMP- TION (100aA Typ. at Vcc = 24V) I PROTECTION AGAINST FEEDBACK DIS- CONNECTION I THERMAL SHUTDOWN I OUTPUT OVERVOLTAGE PROTECTION I SOFT START FUNCTION TYPICAL APPLICATION CIRCUIT (POWERDIP)
SL27J Price





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SL27J on stock

Characteristic	Symbol	Test condition	Min	Typ.	Max	Unit
Drain-source breakdown voltage	BVDSS	VGS=OV, ID=50ccA	800			V
		VDS=Max., Rating, VGs=OV			250
Zero gate voltage drain current	IDSS	VDs=0.8Max., Rating, VGS=OV TC=125IC			1000	o
Static drain-source on resistance (note)	RDS(ON)	VGS=10V, ID=0.5A		4	5	l
Forward transconductance (note)	gfs	VDs=50V, ID=0.5A	1.5	2.5		S
Input capacitance	Ciss			779
Output capacitance	Coss	VGS=OV VDS=25V, f=lMHz		75.6		pF
Reverse transfer capacitance	Crss	VGS=OV VDS=25V, f=lMHz		24.9		pF
Turn on delay time	td(on)	VDD=0.5BVDSS, ID=1.OA		40
Rise time	tr	(MOSFET switching time are essentially		95		nS
Turn off delay time	td (off)	independent of		150
Fall time	tf	operating temperature)		60
Total gate charge (gate-source+gate-drain)	Qg	VGS=10V, ID=1.OA, VDS=0.5BVDSS (MOSFET			34
Gate-source charge	Qgs	switching time are essentially independent of		7.2		nC
Gate-drain (Miller) charge	Qgd	operating temperature)		12.1		nC

ENCODE Input The ENCODE input is fully TTL/CMOS compatible with a nominal threshold of l.5 V. Care was taken on the chip to match clock line delays and maintain sharp clock logic transi- tions. Any high speed A/D converter is extremely sensitive to the quality of the sampling clock provided by the user. This ADC uses an on-chip sample-and-hold circuit which is essen- tially a mixer. Any timing jitter on the ENCODE will be com- bined with the desired signal and degrade the high frequency performance of the ADC. The user is advised to give commen- surate thought to the clock source.

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