| May 2002 PAIRCHILD Revised May 2002 SEMICONDUCTOF~Th/ 74LVT322373 . 74LVTH322373 Low Voltage 32-Bit Transparent Latch with 3-STATE Outputs and 2sl Series Resistors in the Outputs General Description Features The LVT322373 and LVTH322373 contain thirty-two non- s Input and output interface capability to systems at inverting latches with 3-STATE outputs and are intended 5V Vcc for bus oriented applications. The device is byte controlled. Jshold data inputs eliminate the need for external The flip-flops appear transparent to the data when t/:9t s al:Lu;::u[presisto'stoho'dunusedinputs(74LVTH322373). Latch Enable (LE) is HIGH. When LE is LOW, the data that so available without bushold feature (74LVT322373) meets the setup time is latched. Data appears on the bus when the Output Enable (OE) is LOW. When OE is HIGLs s Live insertion/extraction permitted the outputs are in a high impedance state. s Power Up/Down high impedance provides glitch-free The LVTH322373 data inputs include bushold, eliminating bus loading the need for external pull-up resistors to hold unused s Outputs include equivalent series resistance of 2sl t inputs. make external termination resistors unnecessary and These latches are designed for low voltage (3.3V) Vcc reduce overshoot and undershoot applications, but with the capability to provide a TTL intcc s ESD performance: face to a 5V environment. The LVT322373 and Human-body model> 2000V LVTH322373 are fabricated with an advanced BiCMOS Machine model> 200V technology to achieve high speed operation similar t0 5V Charged-device model > 1000V ABT while maintaining a low power dissipation. s Packaged in plastic Fine-Pitch Ball Grid Array (FBGA) Ordering Code: |
| Order Number | Package Number | Package Description |
| 74LVT322373G (Note l) (Note 2) | BGA96A (Preliminary) | 96-Ball Fine-Pitch Ball Grid Array (FBGA), J EDEC M0-205, 5.5mm Wide |
| 74LVTH322373G (Note l) (Note 2) | BGA96A | 96-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC M0-205, 5.5mm Wide |
| Note l: Ordering CodeG indicates Trays Note 2: Devices also available in Tape and Reel Specify by appending the suffix letter "X" to the ordering code Logic Symbol II I I II I II II I I II I I II I II I I II II I II I |
| 0 O | lO il i2 i3 i4 i5 i6 i7 i8 i9 110 ill l12 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 OEi OE3 OE2 0E4 LE, LE3 LE2 LE4 O0 01 02 03 04 05 06 01 08 09010011012013014015016017018019020021022023024025026027028029030031 | 3 |
| I I III I II II I I II I III III I III II I II I |
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N DELAY -. PART NO. DELAY i - 43A-025 25 43A-050 50 - 43A-075 75 -- 43A-100 100 -- - 43A-125 125 -- 43A-150 150 -- - 43A-200 200 - 43A-250 250 43A-300 300 43A-400 400
SUM7962 on stock| | | | | | | | | | | | cE | | 2V | |
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| | | Ta: | -7 | 50< | | | | | | | | | | | |
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| | | | | | | | | | | | | | | | Collector Current,Ic - A |
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The LH28F004SU-LC is specified for a maximum access time of 120 ns (tACC) at 3.3 V operation (3.0 to 3.6 V) over the commercial temperature range (0 to +700C). A corresponding maximum access time of 160 ns (tACC) at 2.7 V (0 to +700C) is achieved for reduced power consumption applications.
