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Part Numbert Mfg Packt D/C Descriptiont Qty Company/Contact  
SUMMIT-S93X6XS02     Kewei    429 
    Nuoxinyuan Electronics Co.,Ltd
  • Contact:Regina
  • Tel:86-755-83957733
  • Fax:86-755-83956848
  • Email: regina@nxy-ic.com
SUMMIT-S93X6XS02         456 
    Phenix Electronics Co.,Ltd
  • Contact:ranie
  • Tel:0-850-30789169
  • Fax:
  • Email: sales@phenixele.hk
SUMMIT-S93X6XS02 EXTREMENETW  SMD-8  03 04    429 
    H.K.YFXK ELECTRONIC CO., LIMI..
  • Contact:suki.zhang
  • Tel:86-0755-83653084
  • Fax:86-0755-83653745
  • Email: suki.fang88@gmail.com
SUMMIT-S93X6XS02 429         
    Rolics Technology Ltd
  • Contact:jason
  • Tel:86-755-83014335
  • Fax:075583014447
  • Email: jason@hkrolic.com
SUMMIT-S93X6XS02     07+    429 
    Everchips International Co., L..
  • Contact:mr
  • Tel:86-755-52683513
  • Fax:+86-755-8398 5207
  • Email: ffxyz@everchips.com

SUMMIT-S93X6XS02 Datasheet
Dl0 (Pin 3): This pin is the common connection between the cathode and anode of two internal diodes. The remain- ing terminals of the two diodes connect to ground. In a grounded-lamp configuration, Dlo connects to the low voltage side of the lamp. Bidirectional lamp current flows in the Dlo pin and thus the diodes conduct alte rnately on half cycles. Lamp currentis controlled by monito ring one- half of the average lamp current. The diode conducting on negative half cycles has one-tenth of its current dive rted to the CCFL Vc pin. This current nulls against the source
SUMMIT-S93X6XS02 Price

PARAMETER SYMBOL MIN TYP. MAX UNIT
High Level Input Voltage VIH 3.0 5.0 V
Low Level Input Voltage VIL 0 1.5 V
High Levellnput Current IlH 10 UA
Low Level Input Current IlL 10 UA
Low Level Output Voltage (3mA at SDA pin) VOL 0 0.4 V
Maximum Output Current IOL -3.0 mA
Maximum Clock Frequency fSCL 0 100 kHz
Data Change Minimum Waiting Time tBUF 4.7 IJs
Data Transfer Start Minimum Waiting Time LHDS1_A 4.0 IJs
Low Level Clock Pulse Width tLOW 4.7 l~ls
High Level Clock Pulse Width l HIGH 4.0 IJs
Minimum Start Preparation Waiting Time LSU Sl_A 4.7 IJs
Minimum Data Hold Time LHD:DAT 5.0 IJs
Minimum Data Preparation Time LSUDAT 250 ns
Rise Time tR 1.0 US
Fall Time tF 300 ns
Minimum Stop Preparation Waiting Time LSUST0 4.7 l~ls


SUMMIT-S93X6XS02 on stock

Pin Name(s) of Pins Input / Output Function
Address D ataI RESET IRQ2 BR2 BG PMS DMS BMS RD WR MMAP CLKIN, XTAL CLKOUT VDD GND SPORT 0 SPORT1 or Interrupts & Flags: IRQO (RFSl) IRQl ( TFSl) FI (DRl) FO (DTl) 14 24 1 1 1 1 1 1 1 1 1 1 2 1 5 5 1 1 1 1 O I/O I I I O O O O O O I I O I/O I/O I I I O Address outputs for program, data and boot memory. Data I/O pins for program and data memories. Input only for boot memory, with two MSBs used for boot memory addresses. Unused data lines may be left floating. Processor Reset Input External Interrupt Request #2 External Bus Request Input External Bus Grant Output External Program M emory Select External Data M emory Select Boot Memory Select External M emory Read Enable External Memory Write Enable Memory M ap Select Input External Clock or Quartz Crystal Input Processor Clock Output Power Supply Pins Ground Pins Serial Port o Pins ( TFS O, R FS O, DTO, DR O, SCLK O) Serial Port l Pins (TFSl, RFSl, DTl, DRl, SCLKl) External Interrupt Request #0 External Interrupt Request # 1 Flag Input Pin Flag Output Pin


=+1
1
jj 1i =A1 /=+2
A\ _--5 J 7
- Supply=+5.OV | 1 L _ INPUT=.30dBm=20mV
| | RL=500C)
| | | - CL=5pF
I | | IIIIIIIII