| Part Numbert | Mfg | Packt | D/C | Descriptiont | Qty | Company/Contact | |
| SUP50N06-25 | 15000 |
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| SUP50N06-25 | 15000 |
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| SUP50N06-25 | RADRA | 02+ | 220 | 15000 |
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| SUP50N06-25 | RADRA | 220 | 02+ | 15000 |
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SUP50N06-25 Datasheet GENERAL DESCRIPTION The ADP3166 is a highly efficient, multiphase, synchronous buck switching regulator controller optimized for converting a 12 V main supply into the core supply voltage required by high performance AMD processors. It uses an internal 5-bit DAC to read a voltage identification (VID) code directly from the pro- cessor, which is used to set the output voltage between 0.8 V and l.55 V. The ADP3166 also uses a multimode PWM architecture to drive the logic-level outputs at a programmable switching frequency that can be optimized for VRM size and efficiency. The phase relationship of the output signals can be programmed to provide 2-, 3-, or 4-phase operation, allowing for the construction of up to four complementary buck switch- ing stages. SUP50N06-25 Price
SUP50N06-25 on stock T he duty cycle ofthe encode clock for the AD 9022 is critical for obtaining rated performance of the AD C. Internal pulsewidths within the track-and-hold are established by the encode com- mand pulsewidth; to ensure rated performance, minimum and maximum pulsewidth restrictions should be observed. Operation at 20 M SPS is optimized when the duty cycle is held at 55%. Because the PROG pin is in a closed-loop signal path the pole frequency must be kept high enough to maintain adequate AC stability. This means that the maximum resistance and capacitance presented to the PROG pin must be limited. See the Stability section for more details. |
