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SUP70N03S Datasheet

Control Input		Signal Path State
A	B	RFC to:
Low	High	RF1
High	Low	RF2

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SYMBOL	CHARACTERISTICS	TEST CONDITIONS	MIN	TYP	MAX	UNITS
Pout Pin Pg llc VSWR	Power Out Power Input Power Gain Collector Efficiency Load Mismatch Tolerance	F = 1025-1150 MHz Vcc = 50 Volts PW = 10 ccsec DF = 1% F = 1090 MHz	150 7.8	8.3 40	25 201	Watts Watts dB %

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Parameter		Symbol	Conditions	MIN	TYP	MAX	Unit
	PT4110	Ic	'2 Ec = ImW/cm2	4.0		25	mA
Collector current	PT4110F	Ic	VcE = SV	2 5		19	mA
Dark current		Icco	Ec = 0, VCE = 10V			1 0	oCA
Collector-emitter saturation voltage		V CL(sat)	'2 Ec = ImW/cm2 Ie = 2.5mA			1.2	V
Collector-emitter breakdown voltage		BVCEO	Ie = O.lmA '2 EC = 0	35			V
Emitter-collector breakdown voltage		BVECO	IE = O.OlmA '2 Ee = 0	6			V
	PT4110				800
Peak sensitivity wavelength	PT4110F				860		nm
	Rise Time	tr	VCE = 2V,Ie = lOmA		60		ceS
Response tirue	Fall Time	tf	RL = ioo I		53		ceS
Halfintensity angle					70

To ensure that the signal applied to the WM8150 VINP pin lies within the valid input range (OV to VDD) the CCD output signal is usually level shifted by coupling through a capacitor, CIN When active, the RLC circuit clamps the WM8150 side of this capacitor to a suitable voltage during the CCD reset period. The RLCINT register bit controls is used to activate the Reset Level Clamp circuit.

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