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The mutual constraints between the maximum operating frequency and the total delay in generat- ing the M input sig nal can be deduced by considering an example. Figure 3 shows an 11C83 driving the clock input of a 9LS161 Modulo-16 Counter. The table shows that the 9LS161 counts up from 5 t0 8 and then presets back t0 5 to re peat the sequence. Its Q2 and 03 0utputs drive the Preset Enable of the 9LS161 and the M input of the 11C83. The clock input of the 9LS1 61 responds to the positive- going edge of the 11C83 0utput and, thus, it is appropriate to evaluate delays from to of Figure 2. The indicated tPUH consists of a worst-case delay of 25 ns, plus the time to rise to the l.3 V level at the 9LS161 input. For a stray capacitance of 10 pF, this rise will not exceed 10 ns. Thus the tPLH in Figure 2 will be 35 ns or less.
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