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SVR02K Datasheet INPUT CAPTURE MODE In this mode, the timer counts down at the instruction clock rate. When an external edge occurs on pin G3, the value in the timer is copied into the capture register. Consequently, the time of an external edge on the G3 pin is "captured". Bit 5 0f the CNTRL register is used to select the polarity of the external edge. This external edge capture can also be pro- grammed to generate an interrupt. The duration of an input signal can be computed by capturing the time of the leading edge, saving this captured value, changing the capture edge, capturing the time of the trailing edge, and then sub- tracting this trailing edge time from the earlier leading edge time. The Input Capture mode is shown in Figure 9. SVR02K Price
SVR02K on stock
requirements is transferred to the Q outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When the clock input is at either the high or low level, the D input signal has no effect ar the output. |
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