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SW20298K Datasheet An internal l.024V precision bandgap reference sets the full-scale range of the ADC to +0.512V. A flexible reference structure allows the MAX1193 to use its inter- nal reference or accept an externally applied reference for applications requiring increased accuracy. SW20298K Price * Allparameters measured atTc=250C,nominalinputvoltage and full rated load unless otherwise noted. Refer to the CALEX Application Notes for the definition of terms, measurement circuits and other information. (1) Noise is measured per CALEX application notes. Measurement bandwidth is 0-20 MHz. RMS noise is measured over a 0.01-1 M Hz bandwidth. To sim ulate standard PCB decou pling practices, output noise is measured with a 10pf, tantalum and O.OlpF, ceramic capacitor located l inch away from the converter. Input ripple is measured into a 10pH source impedance. SW20298K on stock . 2 1 3 l l - l - l 3 . 5 i r - ~ 1 r t . r l r l . O I N N N ~ l t l C O l . O t r n ~ l * ~ - l 5 i c o i 3 l . O t - f l - l * N 1 2 l l I I I I o l r - . r - i 5 l - t - I O l I o l < l . o O . I H l c n i r - I H l l . r l ~ ~ N N I l I 5 i i L r , I I I 1 N I e n . 3 . - t I I I l I I . o l o l . o . c . l . 1 1 . H . c t l Single supply with operation from 2.5 t0 5.5V Low power CMOS technology - 1 mA active current typical - 10. standby current typical at 5.5V Organized as a single block of 128 bytes (256 x 8) Hardware write protection for entire array (24LC024) 2-wire serial interface bus, 12C compatible 100kHz and 400kHz compatibility Page-write buffer for up t0 16 bytes Self-timed write cycle (including auto-erase) 3.5 ms typical write cycle time for page write Address lines allow up to eight devices on bus 10,000,000 erase/write cycles guaranteed ESD protection > 4,OOOV Data retention > 200 years 8-pin PDIP, SOIC or TSSOP packages Available for extended temperature ranges |
