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SW90V2SP1 Datasheet

		I T^=250C
		TC=	2.5vs
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SW90V2SP1 Price

	(l) Te = TH {2} With a 50x50x2mm
	Al htae sink 13) Without heat sink
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SW90V2SP1 on stock

To drive the device from an external clock source, XTALl should be driven while XTAL2 is left unconnected. There are no requirements on the duty cycle of the external clock signal, because the input to the internal clock circuitry is through a divide-by-two flip-flop. However, minimum and maximum high and low times specified in the data sheet must be observed.

			Limits
Characteristic	Symbol	Test Conditions	Min. Typ. Max.	Units
Output Breakdown Voltage	V(BR)DSX	10 =1 mA	50	V
Off-State Output	IDSX	VO=40 V	0.1 1.0	yA
Current	IDSX	VO = 40 V, TA = 1250C	0.2 5.0	LLA
Static Drain-Source	rDScon)	IO=350 mA	1.0 1.5	Q
On-State Resistance	rDScon)	IO = 350 mA, TA = 1250C	1.7 2.5	Q
Source-to-Drain Diode Voltage	VSD	l= 350 mA	1.0	V
Nominal Output Current	10(nom)	VDS(on) = 0.5 V, TA = 850C	350	mA
Output Current	10(chop)	lo at which chopping starts, Tc = 250C	0.6 0.8 1.1	A
Logic Input Current	JlH	VI=VDD	1.0	yA
Logic Input Current	lIL	Vl=0	1O	LLA
SERIAL-DATA	VOH	IOH=-20 hcA	4.9 4.99	V
Output Voltage	VOH	IOH=4 mA	4.5 4.7	V
	VOL	IOL=20 hcA	0 0.1	V
	VOL	101=4 mA	0.3 0.5	V
Prop. Delay Time	tPLH	IO = 350 mA, CL = 30 pF	1 00	ns
Prop. Delay Time	tPHL	10 = 350 mA, CL = 30 pF	60	ns
Output Rise Time	tr	10 = 350 mA, CL = 30 pF	55	ns
Output Fall Time	tf	IO = 350 mA, CL = 30 pF	40	ns
Supply Current	IDD(off)	Outputs OFF	0.5 5.0	mA
Supply Current	IDD (fclk)	fclk = 5 MHz, CL = 30 pF, Outputs OFF	1.3	mA

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