SWI1008CTR75J Datasheet| | | | 70+02 ' L _ | o | 0 4±01 | | | | | | _L } | | | | l X l | | | | | × | | | 11 20 1 5 | 2 0 2 5 | n | | | rrn rn | l rr | | | 10-0210_02! 36_02 ! 'l (D ANODE: A1 ANODE:A2 CATHODE: K | | JEDEC | | JEITA | | TOSHIBA 12-9BIA | | | | | | | |
SWI1008CTR75J Price co InGaAs/lnP - PIN-photodiode co Designed for telecommunications applications co Sensitive receiver for the 2nd optical window (1300 nm) co Suitable for bit rates up t0 1.2 Gbit/s co Low junction and low package capacitance co Fast switching times co Low dark current co Low noise co Hermetically sealed 3-pin metal case co Optimally coupled singlemode-fiber pigtail co High reverse-current stability from planar structure SWI1008CTR75J on stock| PIN NUMBER | PIN NAME | TYPE | DESCRIPTION | | 1. 26 | VDD | PWR | Power for logic and fixed frequency output buffers. | | 2 | Xl | IN | XTAL or external reference frequency input. This input includes XTAL load capacitance and feedback bias for a 12 - 16 MHz crystal, nominally 14.31818 MHz. | | 3 | X2 | OUT | XTAL output which includes XTAL load capacitance. | | 4. 11, 17, 23 | Vss | PWR | Ground | | 5 | TURBO | IN | Speeds up the 60 and 66.6 MHz by 2.5% (see functionality table). It has an internal pull-up resistor. | | 6,7,9,10 | PCLK(0:3) | OUT | Processor clock outputs which are a multiple of the input reference frequency as shown in the table above. | | 8 | VDD2 | PWR | Power for PCLK output buffers only. This VDD supply can be reduced t0 2.5V for PCLK (0:3) outputs. | | 13, 12 | FS(O:1) | IN | Frequency multiplier select pins. See table above. These inputs have internal pull-up devices. | | 14, 20 | VDD | PWR | Power for BCLK output buffers. | | 15, 16, 18 19, 21, 22 | BCLK(0:5) | OUT | Busclock outputs are fixed at one half the PCLK frequency. | | 24 | DISK | OUT | The DISK controller clock is fixed at 24 MHz (with 14.318 MHZ input) | | 25 | USB | OUT | The USB clock is fixed at 48 MHz (with 14.318 MHz input). | | 28, 27 | REF(O:1) | OUT | REF is a buffered copy of the crystal oscillator or reference input clock, nominally 14.31818 MHz. | | | | |
| Parameter | Symbol | Limits | Unit | | Collector-base voltage | VCBO | 50 | V | | Collector-emitter voltage | VCEO | 20 | V | | Emitter-base voltage | VEBO | 6 | V | | Collector current | lc | 3 | A(DC) | | 5 | A(Pulse)1 | | | | O5 | W | | Collector power dissipation | Pe | 2 0 | W 2 | | Junction temperature | Tj | 150 | oc | | Storage temperature | Tstg | -55 t0 150 | oc | | | | |
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