SXA-3318 Datasheet Multiple FLEX 10KE devices can be configured in any ofthe five configuration schemes by connecting the configuration enable (nCE) and con figu ration enable outp u t (nCEO) pin s on each device. Ad ditional FLEX 10K, FLEX 10KA, FLEX 10KE, and FLEX 6000 devices can be configured in the same serial chain. SXA-3318 Price| PART NUMBER | TEMP. RANGE (oC) | PACKAGE | PKG. NO. | | Hll-0506/883 | -55 t0 125 | 28 Ld CERDIP | F28.6 | | Hll-0506-8 | Hi-Rel Pressing with Burn-In | 28 Ld CERDIP | F28.6 | | H14-0506/883 | -55 t0 125 | 28 Ld CLCC | J28.A | | Hll-0507/883 | -55 t0 125 | 28 Ld CERDIP | F28.6 | | H19P0506-9 | -40 t0 85 | 28 Ld SOIC | M28.6 | | H13-0506-5 | O t0 75 | 28 Ld PDIP | E28.6 | | Hll-0506-7 | 0 t0 75 +96 Hour Burn-In | 28 Ld CERDIP | F28.6 | | H19P0506-5 | O t0 75 | 28 Ld SOIC | M28.3 | | Hll-0506-5 | O t0 75 | 28 Ld CERDIP | F28.6 | | Hll-0506-4 | -25 t0 85 | 28 Ld CERDIP | F28.6 | | Hll-0506-2 | -55 t0 125 | 28 Ld CERDIP | F28.6 | | Hll-0507-8 | Hi-Rel Pressing with Burn-In | 28 Ld CERDIP | F28.6 | | H14-0507/883 | -55 t0 125 | 28 Ld CLCC | J28.A | | Hll-0507-4 | -25 t0 85 | 28 Ld CERDIP | F28.6 | | H14P0507-5 | O t0 75 | 28 Ld PLCC | N28.45 | | H19P0507-5 | O t0 75 | 28 Ld SOIC | M28.3 | | Hll-0507-5 | O t0 75 | 28 Ld CERDIP | F28.6 | | H13-0507-5 | O t0 75 | 28 Ld PDIP | E28.3 | | H19P0507-9 | -40 t0 85 | 28 Ld SOIC | M28.3 | | Hll-0507-2 | -55 t0 125 | 28 Ld CERDIP | F28.6 | | Hll-0508/883 | -55 t0 125 | 16 Ld CERDIP | F16.3 | | | | |
SXA-3318 on stock a l q P I P a d a J ( l n d u l s s a j P P V u o ! l e u ! l s a o a l o f i : ) ) s a u u ! l ' x e y \ j | SCON Address = 98H Reset Value = 0000 0000B Bit Addressable | | | SMO/FE | SM1 | SM2 | REN | TB8 | RB8 | TI | Rl | | | Bit: 7 6 5 4 3 2 1 0 (SMODO = 0/1)' Symbol Function FE Framing Error bit. This bit is set by the receiver when an invalid stop bit is detected. The FE bit is not cleared by valid frames but should be cleared by software. The SMODO bit must be set to enable access to the FE bit. SMO Serial Port Mode Bit 0, (SMODO must = 0 to access bit SMO) SMl Serial Port Mode Bit 1 SMO SMl Mode Description Baud Rate" 0 0 0 shiftregister fosc/12 0 1 1 8-bit UART variable 1 0 2 9-bit UART fosc/64 0rfosc/32 1 1 3 9-bit UART variable SM2 Enables the Automatic Address Recognition feature in Modes 2 0r 3. If SM2 = 1 then Rl will not be set unless the received 9th data bit (RB8) is l, indicating an address, and the received byte is a Given or Broadcast Address. In Mode l, if SM2 = 1 then Rl will not be activated unless a valid stop bit was received, and the received byte is a Given or Broadcast Address. In Mode 0, SM2 should be 0. REN Enables serial reception. Set by software to enable reception. Clear by software to disable reception. TB8 The 9th data bit that will be transmitted in Modes 2 and 3. Set or clear by software as desired. RB8 In modes 2 and 3, the 9th data bit that was received. In Mode l, if SM2 = 0, RB8 is the stop bit that was received. In Mode 0, RB8 is not used. TI Transmit interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or at the beginning of the stop bit in the other modes, in any serial transmission. Must be cleared by software. Rl Receive interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or halfway through the stop bit time in the other modes, in any serial reception (except see SM2). Must be cleared by software. NOTE: 'SMODO is located at PCON6. "fOSC = oscillator frequency SU00043 | | | | | | | | | | |
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