| 1 | Rev : C Amendment:/2 Issue Date: January 2000 |
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1. Apply power and keep CKE/RESET at low state ( All other inputs may be undefined) - Apply VDD and VDDQ simultaneously - Apply VDDQ before Vref. ( Inputs are not recognized as valid until after VREF iS applied ) 2. Required minimum 100us for the stable power before RESET pin transition to HIGH - Upon power-up the address/command active termination value will automatically be set based off the state of RESET and CKE - On the rising edge of RESET the CKE pin is latched to determine the address and command bus termination value. If CKE is sampled at a zero the address termination is set t0 1/2 0f ZQ. lf CKE is sampled at a one the address termination is set to ZQ. - RESET must be maintained at a logic LOW level and CS at a logic high value during power-up to ensure that the DQ outputs w be in a High-Z state, all active terminators off, and all DLLs off. 4. Minimum 200us delay required prior to applying any executable command after stable power and clock. 5. Once the 200us delay has been satisfied, a DESELECT or NOP command should be applied, then RESET and CKE should be brought to HIGH, 6. Issue a PRECHARGE ALL command following after NOP command. 7. Issue a EMRS command (BAIBAO="01") to enable the DLL. 8. Issue MRS command (BAOBAl = "00") to reset the DLL and to program the operating parameters. 20K clock cycles are required between the DLL to lock. 9. Issue a PRECHARGE ALL command 10 . Issue at least two AUTO refresh command to update the driver impedance and calibrate the output drivers.
