SY0H646LJC Datasheet In addition to the thermal environment (sealed enclosure, ventilated, open frame, etc), the maximum power capability of LinkSwitch in a given application depends on transformer core size, efficiency, primary inductance tolerance, minimum specified input voltage,input storage capacitance, o utput voltage, output diode forward drop, etc., and can be different from the values shown in Table l. SY0H646LJC Price| CHARACTERISTIC | SYMBOL | TEST CONDITION | MIN | TYP | MAX | UNIT | | Gate Cut-off Current | IGSS | VGS=25V, VDS=O | | | 1O | nA | | Gate-Drain Breakdown Voltage | V (BR) GDS | VDS=0, IG=lOOpA | 25 | | | V | | Drain Current | IDSS (Note) | VDS= -10V, VGS=O | - 2.6 | | -20 | mA | | Gate-Source Cut-off Voltage | V GS (OFF) | VDS = -10V, ID = - O.liuA | 0.15 | | 2O | V | | Forward Transfer Admittance | IYfsl | VDS= -10V, VGS=O, f=lkHz | 8 | 22 | | mS | | Input Capacitance | Ciss | VDS = -10V, VGS = 0, f=lMHz | | 105 | | pF | | Reverse Transfer Capacitance | Crss | VDG= -10V, ID=O, f=lMHz | | 32 | | pF | | Noise Figure | NF (1) | VDS = -10V, ID = -1mA, RG=lkfl, f=lOHz | | 1.0 | 10 | dB | | NG (2) | VDS = -10V, ID = -lmA, RG=lkfl, f=lkHz | | O5 | 2 | | | | | | | |
SY0H646LJC on stock| Power Supply Voltage | Vcc | 4.5 | 5.0 | 5.5 | Volts | | Power Supply Current | lcc (on-hook) lcc (off-hook) | | 28.0 68.0 | 50.0 100.0 | mA mA | | High Levellnput Voltage | Vih | 2.0 | | | Volts | | Low Level Input Voltage | Vil | | | 0.8 | Volts | | High Level Output Voltage | Voh | 3.5 | | | Volts | | Low Level Output Voltage | Vol | | | 0.4 | Volts | | Leakage Current | | | | ±1.0 | uA | | | | | | |
| PARAMETER | SYMBOL | TEST CONDITIONS | MIN | TYP | MAX | UNIT | | Overall System Specification Including CDS, PGA, OFFSET and ADC Functions. | | Full-scale input voltage range (see Note l) | | Max Gain Min Gain | | 0.2 2.04 | | Vp-p Vp-p | | Input signal limits (see Note 2) | VIN | | 0 | | AVDD | V | | Full-scale transition error | | Gain = OdB; PGA[7:0] = 4B(hex) | | 20 | | mV | | Zero-scale transition error | | Gain = OdB; PGA[7:0] = 4B(hex) | | 20 | | mV | | Differential non-linearity | DNL | | | 0.5 | | LSB | | Integral non-linearity | INL | | | 2 | | LSB | | Channel to channel gain matching | | | | 1 | | % | | References | | Upper reference voltage | VRT | | 1 625 | 1 725 | 1 825 | V | | Lower reference voltage | VRB | | 0 900 | 0 975 | 1 050 | V | | Input return bias voltage | VRX | | O60 | 0.65 | 0 70 | V | | Di. reference voltage (VRT-VRB) | VRTB | | 0.65 | 0.75 | 0 85 | V | | Output resistance VRT, VRB, VRX | | | | 1 | | l | | VRLC/Reset-Level Clamp (RLC) | | RLC switching impedance | | | | 140 | | l | | VRLC short-circuit current | | | | 5 | | mA | | VRLC output resistance | | | | 2 | | l | | VRLC Hi-Z leakage current | | | | <0.1 | | | | RLCDAC resolution | | | | 4 | | bits | | RLCDAC step size, RLCDAC = 0 | VRLCSTEP | | | 0.16 | | V/step | | RLCDAC step size, RLCDAC = 1 | VRLCSTEP | | | O09 | | V/step | | RLCDAC output voltage at code O(hex), RLCDACRNG = 0 | VRLCBOT | | | 0.25 | | V | | RLCDAC output voltage at code O(hex), RLCDACRNG = 1 | VRLCBOT | | | O2 | | V | | RLCDAC output voltage at code F(hex), RLCDACRNG = 0 | VRLCTOP | | | 2.75 | | V | | RLCDAC output voltage at code F(hex), RLCDACRNG = 1 | VRLCTOP | | | 1.7 | | V | | Offset DAC | | Resolution | | | | 8 | | bits | | Differential non-linearity | DNL | | | 0.1 | | LSB | | Integral non-linearity | INL | | | 0.25 | | LSB | | Step size | | | | 1.02 | | mV/step | | Output voltage | | Code OO(hex) Code FF(hex) | | -130 +130 | | mV mV | | Programmable Gain Amplifier | | Resolution | | | | 8 | | bits | | Gain | | | | 208 283-PGA[7:0] | | VN | | Max gain, each channel | GMAX | | | 7.4 | | VN | | Min gain, each channel | GMIN | | | 0.74 | | VN | | Gain error, each channel | | | | 1 | | % | | | | | | | |
|
