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SY100ELT24 Datasheet
Self-excitation In the event of a LIN bus fault, the voltage regulator is capable of self-excitation if a phase voltage and frequency of greater than 0.6VAND 1200 Generator RPM is detected. This signal is only possible if the residual magnetism in the alternator rotor core is sufficient enough to generate a magnetic field capable of inducing the voltage signal in the stator windings. If this signal is detected, the regulator will apply an 18.75% duty cycle until the cut-in phase signal is recognized at which time the regulator will soft start ramp to default regulation. The regulator will return to sleep mode at any time when the phase signal has timed out as described above.
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DESCRIPTION The Max247TM package is a new high volume power package exibiting the same footprint as the industry standard T0-247, but designed to accomodate much larger silicon chips, normally supplied in bigger packages such as T0-264. The increased die capacity makes the device ideal to reduce component count in multiple paralleled designs and save board space with respect to larger packages.
SY100ELT24 on stock
The AM55-0023 has two sets of Vdd pins. VDDAl,2 ,3 and VDDBl,2,3. VDDA should be supplied with 5 V. This voltage is internally stepped down t0 3 V to reduce current consumption. If current consumption is not a concern OR only 3 V is available to the part then the VDDB pins should be used. Using the VDDB pins with 5 V will also give greater IP3/IMD performance (See graphs).

Limits
Symbol Parameter Test conditions Min Typ Max Unit
V (BR) DSS Drain-source breakdown voltage ID = ImA, VGs = OV 250 v
V (BR) GSS Gate-source breakdown voltage IG = +100ccA, VDS = OV ±30 v
IGSS Gate-source leakage current VGS = +25V, VDS = OV ±10
IDSS Drain-source leakage current VDS = 250V, VGS = OV 1 mA
VGS (th) Gate-source threshold voltage ID = 1rTiA, VDS = 10V 2 3 4 v
rDS (ON) Drain-source on-state resistance ID = 3A, VGS = 10V 0 63 0.80
VDS (ON) Drain-source on-state voltage ID = 3A, VGS = 10V 1 90 2 40 v
yfs Forward transfer admittance ID = 3A, VDS = 10V 2 2 3 5 S
Ciss Input capacitance 370 pF
Coss Output capacitance VDS = 25V,VGS = Oy f= 1MHz 80 pF
Crss Reverse transfer capacitance 16 pF
td (on) Turn-on delay time 15 ns
tr Rise time VDD = 150V ID = 3A, VGS = 10V, RGEN = RGS = sol 22 ns
td (off) Turn-off delay time 50 ns
tf Fall time 26 ns
VSD Source-drain voltage Is = 3A, VGS = OV 1 5 2 0 v
Rth (ch-c) Thermal resistance Channel to case 4 17 IC/W