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Part Numbert	Mfg	Packt	D/C	Descriptiont	Qty	Company/Contact
SY100ELT31ZC	SYNERGY				230	laige technology Contact:helen Tel:86-10-51987761 Fax: Email: laige-9@ic-key.com
SY100ELT31ZC				ICQ#426661950	2	HongKong 99 IC Trade Co.,Ltd. Contact:Weng Tel:86-755-82500640 Fax:86-755-82500640 Email: hk99icsale@yahoo.cn
SY100ELT31ZC	SYNERGY				460	WELL-SOURCECOMPONENTS Contact:Ms.SUSIECHEN Tel:86-755-82811353 Fax:86-755-82811353 Email: susiechen_ws@yeah.net

SY100ELT31ZC Datasheet

Output Sink Saturation (Vin = 4.0 V, ISink = 1.0 mA) (Vin = 1.0 V, ISink = 0.25 mA)	VOL		0 14 0.1	0 4 0 3	V
Output Sink Current (Vin, Reset = 4.0 V)	ISink	7 0	20	50	mA
Output Off-State Leakage (Vin, Reset = 5.0 V) (Vin, Reset = 10 V)	iR(leak)		0 02 0 02	0 5 2 0	¨A
Clamp Diode Forward Voltage, Reset to Input Pin (IF = 5.0 mA)	VF	0 6	0.9	1 2	V

SY100ELT31ZC Price

	DIMENSIONS
REF.	Mimeters		Inches		NOTES
REF.	Min	Max	Min	Max	NOTES
A	3.050	4.500	0.120	0.117	1 - The lead diameter D is not controlled over zone E
B	12.7		0.500		2 - The minimum axial lengh within which the device may be
g C	1.530	2.000	0.060	0.079	placed with its leads bent at right angles is 0.59"(15 mm)
g D	0.458	0.558	0.018	0.022
E		1.27		0.050

SY100ELT31ZC on stock

PARAMETER	SYMBOL	TEST CONDITIONS	MIN	TYP	MAX	UNIT
Overall System Specification (including 16-bit ADC, PGA, Offset and CDS functions)
Conversion Rate		HIGHSPEED =0, HIGHSPEED = 1, MCLK = 24MHz	6	12		MSPS MSPS
Full-scale input voltage range, PGAMODE=O. (see Note l)		Max Gain Min Gain		0 4 4 08		Vp-p Vp-p
Full-scale input voltage range, PGAMODE=1. (see Note l)		Max Gain Min Gain		0 6 3		Vp-p Vp-p
Input signal limits (see Note 2)	VIN		0		AVDD	V
Full-scale transition error		Gain = OdB; PGA[8:0] = 96(hex)		20		mV
Zero-scale transition error		Gain = OdB; PGA[8:0] = 96(hex)		20		mV
Differential non-linearity	DNL			1125		LSB
Integral non-linearity	INL			20		LSB
Total output noise		Min Gain Max Gain		3 9 11		LSB rms LSB rms
Channel to channel gain matching				1		%
References
Upper reference voltage	VRT			2 85		V
Lower reference voltage	VRB			1.35		V
Input return bias voltage	VRX			1.65		v
Diff. reference voltage (VRT-VRB)	VRTB		1 4	1 5	1.6	V
Output resistance VRT, VRB, VRX				1		l
VRLC/Reset-Level Clamp (RLC)
RLC switching impedance				50		l
VRLC short-circuit current				2		mA
VRLC output resistance				2		l
VRLC Hi-Z leakage current		VRLC = O to AVDD			1	CA
RLCDAC resolution				4		bits
RLCDAC step size, RLCDAC = 0	VRLCSTEP	AVDD= 5.OV		O25		V/step
RLCDAC step size, RLCDAC = 1	VRLCSTEP			0 17		V/step
RLCDAC output voltage at code O(hex), RLCDACRNG = 0	VRLCBOT	AVDD= 5.OV		O39		V
RLCDAC output voltage at code O(hex), RLCDACRNG = 1	VRLCBOT			O26		V
RLCDAC output voltage at code F(hex) RLCDACRNG, = 0	VRLCTOP	AVDD= 5.OV		4 14		V
RLCDAC output voltage at code F(hex), RLCDACRNG = 1	VRLCTOP			2.81		V
VRLC deviation				25		mV
Offset DAC, Monotonicity Guaranteed
Resolution				8		bits
Differential non-linearity	DNL			0 1	0.5	LSB
Integral non-linearity	INL			0 25	1	LSB
Step size				2.04		mV/step
Output voltage		Code OO(hex) Code FF(hex)		-260 +260		mV mV

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