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The bus interface logic of the DAC667 consists of four independently addressable latches in two ranks. The first rank consists of three four-bit input latches which can be loaded directly from a 4-, 8-, 12- or 16-bit microprocessor/ microcontroller bus. These latches hold data temporarily while a complete 12-bit word is assembled before loading it into the second rank of latches. This double buffered orga- nization prevents the generation of spurious analog output values while the complete word is being assembled. All latches are level-triggered. Data present when the con- trol signals are logic o will enter the latch. When the control signals return to logic l, the data is latched. A truth table for the control signals is presented in Table I.
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